Asic Design Implementation Cycle

An application-specific integrated circuit (ASIC) ,is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use.

There are different phases in Asic design cycle , We will go through each cycle and understand from basics.

Specification
This is 1st phase of design , In specification , decisions are taken for the feature supports, vendors , requirements , and usage of the product. This information is very important as this is base to start of a ASIC design.

Requirement Gathering 

It is very very important phase as this decide the end product. Understanding over the requirement should be 200% , anything which is having grey shade , should be documented well.
Any change in requirement will delay in product cycle , sometime, it is OK and can be adjust in project schedule but If changes are big in design in term of effort , then impact will be big.

All the requirements should be documented well.
Tools/Vendor selection 
Check the resource availability.

Study Phase
Understand the requirement thoroughly and accordingly make the design specification.

In this phase , design requirements must be documented. A top level block architecture should be presented in document.


Design Domain :

   Image1 : Design domain and perspective 

Asic Design / RTL Design

Next phase of design cycle is RTL coding , either in Verilog or in VHDL.

RTL coding is based on design specification. Between RTL coding and Design Specification , Micro-Architecture document must be prepared.

At this level, Functionality of design should be clear. Basic data flow should be in place.
If more effort is spend on documentation, then RTL coding will take very less effort but if documentation is poor then RTL coding effort will be more if compared.

Verification 

Verification and RTL coding can be started in parallel. 

Verification must be complete before sign off and To say Verification 100% , Code coverage and functional coverage must be 100%. 

This can be divided in 2 parts. 

1. Functional verification.  

2. Gate level verification 

Functional verification is to verify the given specification of a design , there are tools and process to measure the verification. 

Gate level verification is to verify the functionality at synthesized/routed netlist where we run testcase which can toggle maximum gates. This is to verify the timing /setup/hold  checks of sequential elements. 

Physical Design/Implementation Cycle 

This is PNR cycle which can be started with initial version of netlist. The inputs for PNR is netlist , timing constraint , physical constraint and libraries. If synthesis is physical aware then initial floorplan would be required which can be given by using initial netlist. 

There are many things in PNR , like power grid planning , macro placement , usage of multibit registers . 

Static Timing Analysis 

This is the sign-off stage for any chip , static timing analysis include the timing , physical constraint verification like setup /hold / max cap / max transition / etc checks. 

Physical Verification

Physical verification is a process whereby an integrated circuit layout design is verified via EDA software tools to ensure correct electrical and logical functionality and manufacturability. Verification involves design rule check, layout versus schematic, XOR, antenna checks and electrical rule check.

This is the process of ensuring a design's layout works as intended. Steps include design rule checking (DRC) and layout-versus-schematic (LVS) checks. Design rule checking (DRC) determines if a chip layout satisfies a number of rules as defined by the semiconductor manufacturer.

Quality checks : 

There are quality checks at each stage , one must follow the given guidelines. 

Few of them are :  

Formal verification :  LEC checks between RTL , synthesized netlist and routed netlist. 

CLP checks : If design use the UPF then CLP checks are required. 

Lint : This is for RTL quality check. 

CDC : this checks the clock domain crossing. 

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