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Oct 5, 2020

PCIe_Project_Update


Target ->  Design and Verification of PCIe Controller (Data Link Layer ) for Gen1 and Gen2.

Object : Purpose of this project will be learning data link layer of PCIe controller and get industrial experience.

Time Duration - 3 weeks ( as much as can be done in this duration)

Start Date - 15-DEC-2020 

Team -> to be decided

Task to be done :

Verification :
  1. Verification Environment for Data Link Layer
  2. BFM for Transaction Layer - Task based
  3. Physical Layer BFM  - Task based

Design :
 1. Data link Layer Feature list
 2. Data Link Layer Interface definition.
 3. Top level Block Diagram.

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Put your name and email ID in comment if you want to be part of this project.
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