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rtl_design_lab - bash

$ compile rtl_top.v -f filelist.f

INFO elaboration complete - 0 errors

INFO timing met at 1 GHz (WNS +0.12)

INFO CDC clean - 0 violations

$ run signoff --all

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Clock Dividers and Multipliers

Q1 How to generate a divide by -N clock ?

Generate Divide by 2 Clock - 

Below is circuit for Divide by 2 clock , this is nothing but a T-FlipFlop.

Divide by 3 Clock with 50% duty cycle - 

To generate divide by 3 clock with 50 % duty cycle, you need to use negedge and posedge flops. There is not much logic between the flops, so signals going from posedge to negedge or negedge to posedge , will not be having any timing issue. Half clock cycle will be sufficient to meet the timing. But if frequency is too high , then check gate timing. Half clock cycle may be close to meet timing.

Most solutions that came in, utilized 4 or 5 flip flops plus a lot more logic than I believe is necessary. The solution, which I believe is minimal requires 3 flops - two working on the rising edge of the clock and generating a count-to-3 counter and an additional flop working on the falling edge of the clock.


Below is block diagram which shows the posedge and negedge flops.

Below is RTL code in Verilog, it is not  synthesizable but anyone can make it using reset the flops.

---------------------------
module clk_div_3;

reg clk=0;

parameter PERD = 10 ;
always  #PERD clk = ~clk;
reg [1:0] cnt = 0;
reg cnt_lsb_negedge;

always @(posedge clk)begin
if(cnt == 0)
 cnt <= 2;
         else
  cnt = cnt -1 ;
end
wire cnt_lsb;

assign cnt_lsb = (cnt ==2);

always @(negedge clk)
cnt_lsb_negedge <= cnt_lsb;

real cur_time;
real prev_time;
always @(clk) begin
cur_time <= $time;
  prev_time <= cur_time;
end

wire div_3;
assign div_3 = ~((cnt_lsb) || (cnt_lsb_negedge));

endmodule

----------------------------------------------

Divide by 5 Clock - 

To generate div-5 clock , you can use Mod5 counte 3 flops. there are 2 options.
1st option - for mod5 counter , toggle signal in every 3 count and then 2 count , this will give you div5 clock but duty cycle will be 40/60% .

2nd option -  for 50% duty cycle, you need one negedge flop to detect negedge after count 1 , assuming counter will start from 0.

So here is the logic -

counter --   0 ,1 ,2, 3, 4 ,0, 1, 2 ,3 ,4        --- 60 / 40 % duty cycle
counter --   0 ,1 ,2, 3, 4 ,0, 1, 2 ,3 ,4 ,

at counter value 2, use negedge to detect and then you can use some gates to generate divided by clock.

All odd number divider works on same logic, you just need to pick correct counter to generate clock and optimize logic.

You also need to consider the gate delay here, due to combinational gates , a glitch may propagate to design. Draw your circuit on paper and draw waveform out of it. If there is glitch then your clock divider will not work. Make sure there should not be any glitch.


Clock Multiplier 

Normally we use PLL/DLL  to generate desire clock frequency, but that will come in cost and area. there are other alternative ways to generate clock multiplication , like multiply by 2, use posedge and negedge of clock. If there is a requirement of precise frequency , you can use delay gates and generate clock out of it.




-- Rahul J