Verilog code for 8b/10b encoder and decoder

8b/10b is used mainly for clock recovery in serial communication. With this coding, the serial line will always get a balanced stream of 0's and 1's which give enough switching of 0's and 1's level on the line. It is called DC balancing.
Using this encoding will result in 25% overhead in the data stream , meaning to transmit 80-bits , you will actually transmit 100-bits.

To understand the encoding/decoding , it is highly recommended to read about the "running disparity".


Note that in the following tables, for each input byte, A is the least significant bit, and H the most significant. The output gains two extra bits, i and j. The bits are sent low to high: a, b, c, d, e, i, f, g, h, and j; i.e., the 5b/6b code followed by the 3b/4b code. This ensures the uniqueness of the special bit sequence in the comma codes.

The residual effect on the stream to the number of zero and one bits transmitted is maintained as the running disparity (RD) and the effect of slew is balanced by the choice of encoding for following symbols.

The 5b/6b code is a paired disparity code, and so is the 3b/4b code. Each 6- or 4-bit code word has either equal numbers of zeros and ones (a disparity of zero), or comes in a pair of forms, one with two more zeros than ones (four zeros and two ones, or three zeros and one one, respectively) and one with two less. When a 6- or 4-bit code is used that has a non-zero disparity (count of ones minus count of zeros; i.e., −2 or +2), the choice of positive or negative disparity encodings must be the one that toggles the running disparity. In other words, the non zero disparity codes alternate.
Below is the code for encoder and decoder. Contact me for the soft copy of RTL code.

Encoder Implementation Details ->

Implementation will be based on LUT which can be found in PCIe Specification.

Encoder Pin Descriptions

Name	Type	Descriptions
Clk	I	Encoder Clock. This pin is the main clock of the encoder. All registered inputs and outputs of the encoder are based on the rising of this clock.
Rstn	I	Active Low reset
Data_in[7:0]	I	8-bit data input
kchar	I	Control input
disp_in	I	Running Disparity Input. This pin provides to the encoder the running disparity before the encoding of current 8-bit data on datain_8b bus. 0 - -ve disparity 1 - +ve disparity
data_out[9:0]	O	Encoded data out
disp_out	O	Running disparity output
err	O	Invalid control character requested

Verilog code for 8b/10b encoder
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Verilog code for 8b/10b decoder
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Testbench for the Verilog code , Instantiated encoder and decoder. 

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Ref - https://en.wikipedia.org/wiki/8b/10b_encoding