Digital-design-fundamentals

All topics

Digital Design

Logic building blocks, low-power design, resets and clocking, number systems, error correction and the ASIC flow.

26 articles · 5 groups

Logic & MuxLow Power / UPFResets, Clocks & TimingNumber Systems & ECCFlow & Tools

Logic & Mux 8

• AND, OR Gate Using 2:1 Mux
• Draw a 2-Input NAND Gate Using 2:1 Mux
• How to Make XOR Gate Using NAND
• Which Gate Has Better Power Consumption Than Reversible Logic?
• Type of Adders with Verilog Code
• VHDL Operator
• Pos / Neg Edge Detector
• Lockup Latches

Low Power / UPF 4

• Low Power Design Technique
• Low Power Design and Verification
• UPF Example
• Retention Cells — UPF

Resets, Clocks & Timing 7

• Reset Removal and Recovery Time
• Async Reset or Sync Reset for ASIC?
• Digital PLL
• DLL and PLL
• What is MTBF?
• Asynchronous FIFO with Programmable Depth
• SDC File — A Sample File for Synthesis

Number Systems & ECC 4

• Complex Number
• One's Complement
• Two's Complement
• Error Correction and Detection — SECDEC

Flow & Tools 3

• ASIC Implementation Design Cycle
• Open Source Free CAD / EDA VLSI Tools
• Selective Signal Dumping in VPD / VCS

Back toAll topics Next topicVerilog Tutorial →