What are the various Design constraints used while performing Synthesis for a design ?

1. Timing Constraints

These comes under timing constraints , they are clock constraints like creating_clock, clock 

uncertainity . generative clock , clock latency etc , IO delay, timing exceptions.

Exmaple : 

# Define clock

create_clock -name clk -period 10 [get_ports clk]

# Clock uncertainty (jitter + skew)

set_clock_uncertainty 0.5 [get_clocks clk]

# Clock latency

set_clock_latency 2.0 [get_clocks clk]

# Clock transition

set_clock_transition 0.1 [get_clocks clk]

# Input/Output delays
set_input_delay 2.0 -clock clk [get_ports din]
set_output_delay 1.5 -clock clk [get_ports dout]

# False paths (paths not to be timed)
set_false_path -from [get_cells reg_A] -to [get_cells reg_B]

# Multicycle paths

set_multicycle_path 2 -setup -from [get_cells reg_X] -to [get_cells reg_Y]

# Maximum/Minimum delays

set_max_delay 5.0 -from A -to B

set_min_delay 1.0 -from A -to B

2. Area Constraints

# Set maximum area (in library units)

set_max_area 5000

# Area optimization effort

set_max_area 0   ;# Tool tries to minimize area as much as possible

3. Power Constraints

# Set maximum dynamic power

set_max_dynamic_power 100mW

# Set maximum leakage power

set_max_leakage_power 50uW

# Power optimization mode

set_power_optimization true

 

4. Design Rule Constraints (DRC)

# Maximum fanout

set_max_fanout 16 [get_designs TOP]

# Maximum capacitance

set_max_capacitance 0.5 [get_designs TOP]

# Maximum transition time

set_max_transition 0.4 [get_designs TOP]

5. Environment Constraints

# PVT (Process-Voltage-Temperature) corners

set_operating_conditions WORST   ;# Slow corner

set_operating_conditions BEST    ;# Fast corner

set_operating_conditions TYPICAL ;# Typical corner

# Estimates wire parasitics before place & route

set_wire_load_model -name "wlm_10k" -library tech_lib

set_wire_load_mode top/segmented/enclosed

6. I/O Constraints

# Drive strength of input ports

set_drive      0    [get_ports clk]      ;# Ideal driver

set_drive      1.0  [get_ports din]      ;# Resistance in ohms

# Driving cell (more accurate)

set_driving_cell -lib_cell BUFX4 [get_ports din]

# Output load

set_load 0.1 [get_ports dout]           ;# Capacitance in pF

7. Optimization Constraints

# Compile effort

compile_ultra -effort high

# Boundary optimization

set_boundary_optimization [get_designs TOP] true

# Don't touch / Don't use

set_dont_touch [get_cells critical_inst]

set_dont_use   [get_lib_cells *SLOWCELL*]

# Size only (no topology change)

set_size_only  [get_cells inst_A]

8. Timing Exception Constraints

Constraint	Description
set_false_path	Path excluded from timing analysis
set_multicycle_path	Path allowed multiple clock cycles
set_max_delay	Maximum delay on a path
set_min_delay	Minimum delay (hold) on a path
set_disable_timing	Disable timing arc of a cell

Would you like to see the sample SDC file ? 

Synthesis · Constraints

Sample SDC File

A complete timing-constraint reference for RTL synthesis — clocks, I/O delays & timing exceptions in one file.

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