Understanding Wire Load Models (WLM) in logic synthesis flow.
Synthesis Concept
In the synthesis tool, in order to model the wires we use a concept called Wireload Models.
Wireload models are statistical models with respect to fanout.
Say for a particular technology, based on our previous chip experience we have a rough estimate.
If a wire goes for "n" number of fanout, then we estimate its delay as say "x" delay units.
So a model file is created with the fanout numbers and corresponding estimated delay values.
This file is used while performing Synthesis to estimate the delay for Wires, and to estimate the delay for cells, technology specific library model files will be available.
Why do we need WLM?
- Synthesis happens before Place & Route.
- No physical layout exists, so actual wire lengths are unknown.
- WLM provides a statistical approximation of wire capacitance and resistance based on fanout.
- Allows synthesis tools to optimize cell sizing and buffering realistically.
Key Concepts
- Fanout: Number of loads a net drives.
- Statistical Model: Based on historical data from previous chips in the same technology.
- Estimation: Higher fanout → longer estimated wire → higher delay/capacitance.
- Technology Specific: Different libraries (e.g., 28nm, 7nm) have different WLMs.
How it works in Synthesis
The synthesis tool uses the WLM file to calculate interconnect parasitics for timing analysis.
/* Example logic flow in Synthesis Tool */
1. Define WLM:
set_wire_load_model -name "wlm_28nm"
2. Apply Mode:
set_wire_load_mode "segmented"
3. Synthesis:
compile_ultra
// Tool calculates:
// Wire Delay = f(Fanout)
// Cell Delay = f(Input Slew, Output Load)
Note: WLM is an approximation. After Place & Route, actual wire lengths are extracted (SPEF files), and timing is re-verified with accurate parasitics. WLM is only for pre-layout synthesis.
WLM bridges the gap between logical design and physical reality during synthesis.
Pre-Layout • Approximation • Fanout-Based
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