Serial Peripheral Interface - SPI

Serial Peripheral Interface Bus

The Serial Peripheral Interface (SPI) bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems. The interface was developed by Motorola and has become a de facto standard. Typical applications include Secure Digital cards and liquid crystal displays.

SPI devices communicate in full duplex mode using a master-slave architecture with a single master. The master device originates the frame for reading and writing. Multiple slave devices are supported through selection with individual slave select (SS) lines.

Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses. The SPI may be accurately described as a synchronous serial interface,[1] but it is different from the Synchronous Serial Interface (SSI) protocol, which is also a four-wire synchronous serial communication protocol, but employs differential signaling and provides only a single simplex communication channel.

Single Master Multi Slave

Interface ->
SCLK   -> Clock from master to slave
MOSI   -> Master Out Slave In
MISO   -> Master In Slave Out
SS       -> Slave Select

Data Transmission 

To initiate a transaction, Master first assert slave select line to select the slave.Typical data transmission size is 8-bit , but it can be specific to it's usage and bit size can be anything (Application specific , Master and Slave will have to re-design to support odd size of transaction).

During each SPI clock cycle, a full duplex data transmission occurs. The master sends a bit on the MOSI line and the slave reads it, while the slave sends a bit on the MISO line and the master reads it. This sequence is maintained even when only one-directional data transfer is intended.

Transmissions normally involve two shift registers of some given word size, such as eight bits, one in the master and one in the slave; they are connected in a virtual ring topology. Data is usually shifted out with the most-significant bit first, while shifting a new least-significant bit into the same register. At the same time, Data from the counterpart is shifted into the least-significant bit register. After the register bits have been shifted out and in, the master and slave have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the master stops toggling the clock signal, and typically deselects the slave.


SPI MODE

1. At CPOL=0 the base value of the clock is zero,i.e. the active state is 1 and idle state is 0.

• For CPHA=0, data are captured on the clock's rising edge (low→high transition) and data is output on a falling edge (high→low clock transition).

• For CPHA=1, data are captured on the clock's falling edge and data is output on a rising edge.

2. At CPOL=1 the base value of the clock is one (inversion of CPOL=0), i.e. the active state is 0 and idle state is 1.

• For CPHA=0, data are captured on clock's falling edge and data is output on a rising edge.

• For CPHA=1, data are captured on clock's rising edge and data is output on a falling edge.

A Summary table is given below.

Advantages

• Full duplex communication in the default version of this protocol.
• Push-pull drivers (as opposed to open drain) provide good signal integrity and high speed.
• Higher throughput than I²C or SMBus.
• Complete protocol flexibility for the bits transferred
• Not limited to 8-bit words
• Arbitrary choice of message size, content, and purpose
• Extremely simple hardware interfacing
• Typically lower power requirements than I²C or SMBus due to less circuitry (including pull up resistors)
• No arbitration or associated failure modes
• Slaves use the master's clock, and do not need precision oscillators
• Slaves do not need a unique address — unlike I²C or GPIB or SCSI
• Transceivers are not needed
• Uses only four pins on IC packages, and wires in board layouts or connectors, much fewer than parallel interfaces
• At most one unique bus signal per device (chip select),all others are shared Signals are unidirectional allowing for easy Galvanic isolation.
• Not limited to any maximum clock speed, enabling potentially high speed 

Disadvantages

• Requires more pins on IC packages than I²C, even in the three-wire variant
• No in-band addressing; out-of-band chip select signals are required on shared buses
• No hardware flow control by the slave (but the master can delay the next clock edge to slow the transfer rate)
• No hardware slave acknowledgment (the master could be transmitting to nowhere and not know it)
• No error-checking protocol is defined
• Without a formal standard, validating conformance is not possible
• Only handles short distances compared to RS-232, RS-485, or CAN-bus
• Many existing variations, making it difficult to find development tools like host adapters that support those variations
• SPI does not support hot swapping (dynamically adding nodes)
• Interrupts must either be implemented with out-of-band signals or be faked by using periodic polling similarly to USB 1.1 and 2.0
• Typically supports only one master device (depends on device's hardware implementation)

Table of Contents

Universal asynchronous receiver/transmitter

UART (Universal Asynchronous Receiver/Transmitter)/USIM are used for communication between two devices through serial line. The primary function of UART/USIM is parallel to serial conversion when transmitting and serial-to-parallel conversion when receiving.

Frame Format 

Features

• Full duplex , 5 ,6 ,7, 8 bit mode by configuration
• Even , odd or no parity bit 
• 1, 1,5 ,2 -stop bit 
• Parity Error , Framing Error , Buffer overrun Error 
• Tx/Rx Interrupt 
• Loopack mode (optional)

UART Block Diagram

Based on the system requirement , Tx and Rx can have Async FIFO to transmit/receive data. Before storing in FIFO, data have to go/drive from shift register , at the end of transaction, module can generate a pulse to store data into Rx FIFO or to fetch data from Tx FIFO for next transition.
It is totally depend on implementation.


While implementing the UART Tx and Rx module, both can run at system frequency and with system frequency, one can generate a pulse which is equivalent to Baud rate and this pulse can be used to shift data in register in Tx and Rx. It is also depend on implementation and requirement. If it is Low Power module then whole module can run on low frequency which is baud rate clock so that number of transition will be reduced and dynamic power will be less if compared.

The ideal polarity of line is 1'b1 ( pull up active).

Serial protocol normally depend on the usage and application, for UART also , there are few standard registers which are protocol specific. They are given below.

RBR -> Receive buffer register
THR -> Transmitter holding register
IER  ->  Interrupt enable register
FCR -> Fifo control register
LCR  -> Line control register
MCR -> modem control register
LSR ->  Line status register
MSR -> Modem status register
BRR -> Baud rate register

Implementation of Baud Rate Generator - > 
Baud_Rate_Generator


Types of Error in UART -> 

Framing Error ->  If configured number of stop bit/s not detected.
Parity Error ->   Parity bit mismatch.
Overtun Error -> Rx buffer already having data and Rx still receiving data. No space to store data until data is read by CPU.

Rx can include Timeout error too.

Data Transmission Control ->
Controllable characteristics of the data transmission are ->

• Baud rate 
• Bits per character 
• Type of Parity 
• Number of stop bits
• Transmission termination (optional)

Baud Rate
Standard baud rates supported by most serial ports:
110
300
600
1200
2400
4800
9600
14400
19200
28800
38400
56000
57600
115200

Standard baud rates supported by some serial ports:
128000
153600
230400
256000
460800
921600

Modem Handshaking control 
RS-232C describes how a computer and a modem should interact to ensure that they agree on who is ready to do what.
The modem control register is used to control the outgoing signals used for this protocol.

A Sample of MCR is 0 ->

Handshaking protocolThe computer should set DTR=1 when it is ready for communication. (Setting DTR=0, for example, will cause a modem to hang up the telephone line at the end of a transmission.)

RTS=1 indicates that the computer desires to transmit information. Setting RTS=0 would indicate that the modem should turn the line around when using half-duplex mode. For full-duplex mode, RTS should be permanently 1


Modem Handshaking Status

The modem status register (MSR, accessed via port 6), is used to sense incoming signals used for the handshaking RS-232C protocol. All bits in this register are reset to 0 when the register is read, except as noted below.

DSR=1 indicates that the modem is ready for communication. This bit remains 1 after the register is read if the modem remains ready.

CTS=1 indicates that the computer is allowed to transmit information. In half-duplex mode , the modem responds to a signal RTS=1 from the computer by turning the line around and then setting CTS=1. This bit remains 1 after the register is read if the computer is still allowed to transmit information.

CD=1 if the modem believes that there actually is an incoming signal. For example, if a computer is communicating with a remote terminal over a telephone line, and the modem detects that the other party has hung up, it will set CD=0. This bit remains 1 after the register is read if the modem still believes that there actually is an incoming signal.

The modem sets RI=1 when it detects a ringing signal on the telephone line. Thus RI=1 is a request for service from a remote site.

Questions asked during Interview related to UART 
Q1 How Rx is working ? When will you sample start bit ? 
A. 
Q2 Why there is 16x sampling rate ?
A. 
Q3 How to match baud rate ? 
A. 
Q4. Format of UART frame , why stop bit is 1/1.5/2 ? 
A
Q5 How baud rate is generated ? 
A 
 

Thanks for reading my Blog,please leave your comment if you have any doubt or question.

Table of Contents

I²C (Inter-Integrated Circuit)

Transmitter   ->  This is the device that transmits data to the bus
Receiver         ->  This is the device that receives data from the bus
Multi-master  -> I2C can have more than one master and each can send commands
Synchronization -> A process to synchronize clocks of two or more devices

Slave               ->  This is the device that listens to the bus and is addressed by the master

Master            ->  This is the device that generates clock, starts communication, sends I2C commands and stops communication

Arbitration      -> A process to determine which of the masters on the bus can use it when more masters need to use the bus

Interface

It worked on 2 wire , SCL and SDA. 

Master is responsible for START and STOP condition. 

Serial Data Transfer
For each clock pulse one bit of data is transferred. The SDA signal can only change when the SCL signal is low – when the clock is high the data should be stable.

Modes

Standard mode  : 100 kbit/s

Full speed         :  400 kbit/s

Fast mode         :  1 mbit/s 

High speed        : 3,2 Mbit/s

Applicability of I2C protocol features 

Byte Format 

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

7-bit Addressing Format 

10-bit Addressing Format 

Details on ACK and NACK

ACK ->

The Acknowledge signal is defined as follows: the transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.

Conditions which lead to NACK -> 

1.No receiver is present on the bus with the transmitted address so there is no device to respond with an acknowledge. 

2. The receiver is unable to receive or transmit because it is performing some real-time function and is not ready to start communication with the master. 

3. During the transfer, the receiver gets data or commands that it does not understand. 

4. During the transfer, the receiver cannot receive any more data bytes. 

5. A master-receiver must signal the end of the transfer to the slave transmitter.

Clock stretching 

Clock stretching pauses a transaction by holding the SCL line LOW. The transaction cannot continue until the line is released HIGH again. 

Clock stretching is optional and in fact, most slave devices do not include an SCL driver so they are unable to stretch the clock. On the byte level, a device may be able to receive bytes of data at a fast rate, but needs more time to store a received byte or prepare another byte to be transmitted. Slaves can then hold the SCL line LOW after reception and acknowledgment of a byte to force the master into a wait state until the slave is ready for the next byte transfer in a type of handshake procedure. On the bit level, a device such as a microcontroller with or without limited hardware for the I 2C-bus, can slow down the bus clock by extending each clock LOW period. 

The speed of any master is adapted to the internal operating rate of this device. In Hs-mode, this handshake feature can only be used on byte level,

I2C Interview questions 

Q1. How can I generate a repeated start condition?

Let's assume the following situation: The controller lets the SCL line go high and the device pulls SDA low to acknowledge. So far no problem but how do you generate a repeated start condition now? The device is pulling SDA low.

First you have to complete the ACK cycle. To do this, you must pull SCL low again. The slave will release the data line when it detects that SCL is low. Now you can issue a stop command. To do this, you let the SCL go high again and then pull low the SDA line.

This is the confusing part of the procedure. Normally, you would suspect that by letting the clock line go high again you will be clocking in the first bit of a new byte. As a matter of fact that is the case. But since the chip will detect a START condition, this operation gets cancelled

Q2. Can I abort an ongoing I2C bus transmission?
Is it okay to abort an on-going transmission any time.

According to the specification, this should work. It depends on the layout of the component. A real I2C compatible IC will be able to handle this. It might make sense to test this before you use it.

Usually, when a START or STOP condition is detected, the internal logic of the chip is forced into a certain state. Internally, the logic that detects START and STOP is different from the logic that does all other processing. The START together with the address register is to be considered as a functional unit inside the chip.

When a START is detected, all internal operations are cancelled and the chip will compare the incoming data with its own address.

When a STOP is detected, ALL chips on the bus will reset their internal logic to IDLE mode except for the START detector (this is also used to cut power consumption). Therefore, when a start condition is issued on the bus, the START detector will 'wake-up' the rest of the internal logic.

Q3. Do I need to generate an ACK in read mode on the last byte?
This is a somewhat puzzling question. Indeed this is a bit strange. Usually, if you have read the last byte in a chip and generate an ACK, the chip should do nothing anymore, so the bus should be clear for you to create a STOP condition. Apparently, there are some chips that start transmitting data again. One such chip is the PCF 8574 I/O expander.

Though not always desirable, this feature can come in handy. If you need to sample incoming data fast, then you just continue reading from the chip. This prevents that you lose 'arbitration' of the bus in a multi-master environment.

It also speeds things up. You don't have to address the chip over and over again so you save the time for START, Address, ACK and STOP stage for every next byte read. This can lead to a more than doubled transfer rate.


Q4. Why does the SCL line have to be bi-directional?
The clock line needs to be bi-directional when using a MULTI-MASTER protocol and when using the synchronization protocol.

When you are using only one Master then this is not required since the clock will always be generated by this device. If you run Multi-master then this changes. One master must be able to receive data from another master. At that time it must be able to receive clock information via the clock line also.
How can I monitor the I2C bus?

There are a few commercial I2C monitor / debuggers around that can do this.

There is another possibility to do this: By using the stand-alone I2C controller PCF8584 from Philips. This chip has a certain mode in which it does not take part in the real I2C action but only records what is going on. It listens to all addresses, but does not generate any acknowledge. Using some software routines and a MCU you could build a universal I2C data logger.

Q5.How can I test / debug the I2C bus?

There is no general way to debug an I2C bus. However, a few guidelines might help to get it running.

First thing is to check the levels on the bus. You should see a clear signal that has a low level that is lower then 0.8 volt and a high level which is at least 3.5 volts.

If the high level is not high enough or does not rise fast enough then you can try to lower the value of the pull up resistor. You must take care however not to surpass the maximum allowable current in the I2C driver stage. The minimum allowable resistor for a 5 volt driven I2C bus is 5 V / 3mA = 1600 Ohms. A typical value of 4700 ohm should work fine.

Make sure the bus is not 'stuck' to '0'. This could be the result of a bad power supply (chips go into latch up during power-on) or a bad chip.

There are a few commercial I2C monitor / debuggers around.
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REF - http://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus/frequently-asked-questions/i2c-faq.html
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I2C
1. Can devices be added and removed while the system is running (Hot swapping) in I2C ? ( What is hot swapping in I2C ? )
a practical example is HDMI, which has some high speed IO for the video/sound, and then has I2C for control. If you were designing a monitor, or a video out device, you would need to support the plugging in of one or more monitors.

Hot swap can have issues with master reads in that the master will be ack-ing the read data bytes. If a slave is disconnected during a read, the master will see all 1's for the data bits. Some devices will include a checksum (ideally one where all 1's is not a valid choice) which helps to solve that corner-case.

I2C devices are addressed. If a device is hot swapped with one having the same address, there could be issues. If the master polls devices regularly, then it would be able to detect normal unplug/pluge events. Likewise, some circuits might provide an interupt to the uC for the connect plugged/unplugged.

2. What is the standard bus speed in I2C ?

3. How many devices can be connected in a standard I2C communication ?

4. What are the 2 roles of nodes in I2C communication ?

5. What are the modes of operation in I2C communication ?

6. What is bus arbitration ?

7. Advantages and limitations of I2C communication ?

8. How many wires are required for I2C communication ? What are the signals involved in I2C ?

9. What is START bit and STOP bit ?

10. How will the master indicate that it is either address / data ? How will it intimate to the slave that it is going to either read / write ?

11. Is it possible to have multiple masters in I2C ?

Table of Contents