fusion compiler : balance between timing /cell density and route congestion - floorplanning

Hello ,

Many of front-end engineer doesn't know about the back-end process , which is Ok but would be good if you know what is happening at backend , you can write much better RTL. 

For example, if there is lot of computation happening in the RTL code, it is better to keep it under one module which can be controlled in back-end , like make bound or define max_density to get the desired results. 

An RTL engineer also can think of partitioning of design , which is having advantage and disadvantage , it is a trade-off between time and resource . 

I have also mentioned about the hierarchal synthesis , which means you can synthesize modules and use an abstract view in top level , it will reduce the turn around time ( run time will be less) bu tit will increase gate count as optimization at module boundary would not be effective in this case. 

In the flat synthesis , we give all the RTL module as filelist and synthesize all the modules ,  gate count would be less, floorplan area would be less but tool run time will increase. 

Keep following me, I will try to put more stuff which connect front-end to back-end , as I said , comments are welcome and will try to include the other topics. 

Thanks