Verilog - Lexical Element

Lexical --  it means related to the language, here will describe in more detail about the lexical elements in verilog.

Convention Overview 

This is important because this will let you know how to use verilog construct in RTL coding. Verilog is not much high rule constraint based language ,but to use it , you need to know few basic thing mentioned below.

• operator
• whitespace
• comment
• number
• string
• identifier
• keyword

operator 

Operators are single, double or triple character sequence and used in expression.

Urinary operators appear to be left of their operand.
Binary operators appear between their operands.
A ternary operator has two operator character that separate three operands.

white space and comments 
white space can contain char like space, tab, newlines ,etc
comments , one line comment will start from  //
multiple line comments will start from /* and end with */

number
Constant number can be specified in decimal, hexadecimal, octal or binary format.

exp -
23   // decimal number
'b10101  // binary number
'd23   // decimal number
'hF3  // hex number
'o23 // octal number

This can be divided into sized and unsized number .. sized number will be like 5'h1F  // 5 -bit number

string 
string is a sequence of character enclosed by double quotes and all must be in a single line.
Verilog treats strings used as operand in expression and assignment as a sequence of 8-bit ASCII value.
string manipulation is also possible in verilog but all will be done after converting into ASCII value.

Will not go in much details as we normally don't use those in RTL coding.
Special character in string -

\n  - new line
\t  - tab charc
\\ \character
\" "character
%% %character

identifier 
first character must not be a digit or $ ; it can be a letter or an underscore
lowercase , uppercase letters are considered to be different.

Escaped Identifiers 
Escaped identifiers start with the backslash character (\) and provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal).


keyword 
Keywords are predefined non-escaped identifiers that are used to define the language construct.
Any keyword having escape character in starting , is not considered as Verilog Keyword.
system task includes in keywords.

Text Substitution 
For re-usability of RTL code , one can use `define in RTL and use Macro in RTL instead of constant number.
all define/parameter can be override or defined in a separate file which can used in configuration of design.

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For more information, visit below page.
Verilog - Compiler Directive

Verilog Overview main page -
Verilog Overview


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