RTL DIGITAL DESIGN

Apr 29, 2026

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CONTENTS

1.Introduction :

1.1 Career Growth in VLSI Industry
1.2 The Future of Semiconductor

2. VLSI Topics

2.1  Semiconductor Job Portal - Intern & freshers
2.2  Digital Design for Beginners and Professionals
2.3  Career Growth in VLSI Industry
2.4  The Future of Semiconductor
2.5  Reason for limited entry scope for Freshers in VLSI
2.6  VLSI Industry Update
2,7  List of Semiconductor Companies
2.8  Top 10 VLSI companies
2.9  VLSI Industry Updates
2.10 Engineering Basics
2.11 Open Sourced FREE CAD/EDA VLSI tools

2.12 List of top 10 companies in Semiconductor - 2021

2.13 The best top 20 universities for MS in Digital VLSI in USA

2.14 Solution: Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar

2.15 Question Answer on VLSI Semiconductor

2.16 System on chip architecture

3. Digital Design:

3.1  Low Power Design Technique
3.2  Reset Removal and Recovery Time
3.3  AND , OR gate using 2:1 Mux
3.4  Draw a 2 input NAND gate using 2:1 mux
3.5  Low Power design and verification
3.6  Which gate power consumption better than reversible logic gate?
3.7  UPF Example
3.8  SDC File - A Sample file for Synthesis
3.9  Pos n Neg edge detector
3.10 Lockup Latches
3.11 Selective Signal dumping in VPD VCS
3.12 Async Reset or Sync Reset for ASIC ?
3.13 Digital PLL
3.14 Complex Number
3.15 DLL and PLL
3.16 How to make XOR gate using NAND
3.17 What is MTBF ?
3.18 One's Complement
3.19 Two's Complement
3.20 Error Correction and Detection - SECDEC
3.21 Running Disparity
3.22 Open Sourced FREE CAD/EDA VLSI tools

3.23 Type of Adders with Verilog Code
3.24 VHDL operator
3.25 Asynchronous FIFO with Programmable Depth
3.26 Asic Implementation Design Cycle

3.27 Comparing AMBA AHB to AXI Bus using System Modeling.

3.28 Difference between I2C or CAN protocol ?

3.29 Retention Cells - UPF

4. Semiconductor Interface/Bus Protocols

4.1  List of Protocols (PCIe, USB , etc.)
4.2  I²C (Inter-Integrated Circuit)
4.3  Universal asynchronous receiver/transmitter
4.4  SPI
4.5  PCI-Express - Overview
4.6  Transaction Layer in PCI Express

4.7 Microwire IP Interface

5. Verilog Tutorial /Crash Course

5.1  Verilog Introduction
5.2  Refreshing your brain with Verilog
5.3  Verilog - Data Types
5.4  Verilog - Statements
5.5  Verilog Design Style
5.6  Verilog - System Task
5.7  Verilog Operators
5.8  Verilog - Reserved KeyWords
5.9  Parameterized Modules in Verilog

5.10 Timescale in Verilog

5.11 File Handling in Verilog

5.12 Blocking and Non-Blocking in Verilog

6. RTL Design Code

6.1  Verilog Projects
6.2  RTL Verilog Code for Design
6.3  PCIe_Project_Update
6.4  Verilog Code for the counting number of 1's and 0's
6.5  Verilog code for Asynchronous and Synchronous Reset Flip-Flop
6.6  Verilog code to detect Pattern
6.7  Verilog Code for Gray to Binary Code Converter
6.8  Verilog code for module
6.9  Verilog code for FIR FILTER
6.10 Verilog code for parity checker (even parity/odd parity)
6.11 Verilog code square root of a number
6.12 Verilog Code for Round Robin Algorithm
6.13 Verilog Code for Binary to 7-segment LED converter
6.14 Verilog Code for modules
6.15 Verilog Code for 8-bit ALU
6.16 Verilog Binary to gray code conversion

6.17 Verilog code and FSM design to generating custom waveform

6.18 Verilog code for Synchronous FIFO ( First In First Out )

6.19 SPI Controller

6.20 CRC Generator

7. Clock Domain Crossing (CDC)

7.1  Clock Domain Crossing (CDC)
7.2  Convergence , divergence and re-convergence
7.3  CDC - Real time implementation

8. RTL Lint

8.1 SpyGlass Custom Goal setup
8.2 Synchronizers list dump using SpyGlass Tool

9. STA

9.1 Unateness-> Positive Unate and Negative Unate
9.2 VLSI_EXPERT: Transition Violation in Semiconductor

10. Synthesis

10.1 .lib to/from .db conversion

10.2 fanout report on hierarchy in design in synthesis

10.3 Physical Aware Synthesis

10.4 SDC file for DDR memory

11. Integrated-Circuit Fabrication

11.1 IC Fabrication : Interview Questions / Answers

12. AHB-AXI Protocol

12.1 How do split response and retry work for the AHB protocol?

12.2 Comparing AMBA AHB to AXI Bus using System Modeling.

13. PCIe Protocol

13.1  PCI-Express - Overview
13.2  Transaction Layer in PCI Express
13.3  8b10encoder/decoder
13.4 Running Disparity

14. Solution :Samir Palnitkar : A Guide to Digital Design and Synthesis

14.1 Solution: Verilog HDL A guide to Digital Design and Synthesis - Samir Palnitkar

15. Place holder5

16. DAA

16.1  Left Edge Channel Algorithm for detailed routing
16.2  Dynamic vs Static Timing Analysis
16.3  DAA: Design and Analysis of Algorithm
16.4  DAA: Design and Analysis of Algorithm - QA

17. Scripting/Others

17.1  GNOME - Terminal while login in VNC
17.2  Shell Script Tutorial
17.3  GVIM Help
17.4  List of Perl Scripts used in post data processing

18. Interview Preparation

18.1  VLSI Interview Questions
18.2  Generic interview Questions
18.3  Interview question on AXI protocol
18.4  Implementation of Logical Questions

18.5 Digital Design Interview Question on PCIe express

18.6 Digital Design Interview Question on Synthesis

19. Academic/ Educational Projects with Micro-Architecture and Verilog code

19.1  RoadMap For Academic Projects
19.2  PCI-Express - Overview
19.3  Transaction Layer in PCI Express

19.4 Microwire IP

20. Verification

20.1 Key Points in Mixed Signal Design Verification

21. Physical Design

21.1 What is the difference between a DRC and a DRV in VLSI PD?

21.2 Physical Design - Common Questions

21.3 FILLER CELLS

21.4 Clock buffers and clock interverter

22. General Question:

22.1 Logical Question
22.2 APTITUDE Question for Interviews

22B . VLSI Quiz

22B.1 Quiz1 : Digital Design

22B.2 Quiz2 : Digital Design
22B.2 Quiz 3 : Digital Design
22B.2 Quiz 4 : Digital Design
22B.2 Quiz 1 : UPF
22B.2 Quiz 2 : UPF
22B.2 Quiz 3: UPF
22B.2 Quiz 4 : UPF
22B.2 Quiz UPF : Level Shifter
22B.2 Quiz: UPF : Power Switch

23. Non-VLSI Topics:

23.1  Worst Hiring Stories
23.2  You need to remove these 6 items from your resume asap
23.3  Resume Guideline if you are applying for job as a Freshers.
23.4  10 Things to remember while considering the offers from your next employer
23.5  Are you looking for job change ?
23.6  How to negotiate for the best when making a move from your present employer ?
23.7  where an engineer/fresher can get the job ?

23.8 How to start a academic project

23.9 Team Leadership Score check
23.10 Team Leadership Question/Answer

23.11 Being productive while working from home

24. Salary Around the Globe

24.1 Norway Salary - Average salary for Senior Software Engineer in Norway with 10+ years experience?

24.2 Sweden Salary - An Average salary in Sweden for IT professional

25. Job Opportunities in Norway

25.1 Norway Salary - Average salary for Senior Software Engineer in Norway with 10+ years experience?

25.2 Is it hard to get a job in Norway, as a foreigner?

25.3 Living cost in Norway , compared with India

26. Finland Opportunities in IT Sector

26.1 Moving to Finland from India , is it worth ?

27. Funny Posts ( non technical )

27.1 40+ Photos That Evoke a Lot of Curious Questions and Can’t Be Explained

CORDIC Implementation

What is CORDIC Algorithm ?

The CORDIC (COordinate Rotation DIgital Computer) algorithm is an efficient, iterative method for calculating trigonometric, hyperbolic, logarithmic, and square root functions using only additions, subtractions, and bit shifts. It is highly valued in hardware design (FPGAs, ASICs) and microcontrollers because it eliminates the need for expensive hardware multipliers.

How CORDIC Algorithm Works

Concept: CORDIC computes functions by rotating a 2D vector by smaller and smaller, predetermined angles (pseudo-rotations).
Operations: Instead of complex multiplication, it uses binary shifts (to divide by powers of 2) and adds/subtracts to rotate the vector, making it very fast.
Iterative Process: Through several iterations, the algorithm converges to the desired output, with accuracy improving as more iterations are performed.
Modes:Rotation Mode: Given an input angle, it computes the corresponding sine and cosine components.
Vectoring Mode: Given the
coordinates, it rotates the vector to the
-axis to calculate its magnitude and angle.

Key Features and Applications

Hardware Efficiency: It is ideal for digital signal processing (DSP), digital communication systems, and simple calculators.
Versatility: Beyond basic trigonometry, it is used for Cartesian-to-polar conversions, square roots, and complex multiplications.
Examples: It is implemented in ARM-based processors like the STM32G4, Intel 8087, and Hewlett Packard’s HP-35 calculator.

Jan 7, 2026

UPF : Power Switch

UPF : Power Switch details :

Power Switch in UPF (Unified Power Format) is used to control power gating—i.e., turning a power domain ON or OFF to save leakage power in low-power VLSI designs.

What is a Power Switch?

A power switch represents a set of header (PMOS) or footer (NMOS) transistors that:

• Connect or disconnect a power domain

• Are controlled by enable signals

• Allow blocks to be shut down during idle mode

Why Power Switch is Needed

• Reduce leakage power

• Enable power-gated domains

• Essential for mobile / low-power SoC designs

Where Power Switch is Used

• Between:

• VDD → Power-gated domain (header switch)

• Power-gated domain → VSS (footer switch)

Key UPF Elements Involved

• create_power_domain

• create_supply_port

• create_supply_net

• create_power_switch

• set_domain_supply_net

Simple UPF Power Switch Example :

-----------------

create_power_domain PD_CORE

create_supply_port VDD

create_supply_port VSS

create_supply_net VDD

create_supply_net VSS

connect_supply_net VDD -ports VDD

connect_supply_net VSS -ports VSS

create_power_switch PSW_CORE \

-domain PD_CORE \

-input_supply_port {VDD VDD} \

-output_supply_port {VDD_SW VDD} \

-control_port {PS_EN} \

-on_state {ON PS_EN}

-----------------

Meaning:

• PSW_CORE → Power switch name

• VDD → VDD_SW → Switched power

• PS_EN → Enable signal

• When PS_EN = 1 → Power ON

• When PS_EN = 0 → Power OFF

⸻

Header vs Footer Switch

Type Transistor Position Common Use

Header PMOS Between VDD & block Low noise

Footer NMOS Between block & GND Area efficient

⸻

Power Switch with Isolation & Retention (Typical Flow)

1. Power switch OFF

2. Isolation enabled

3. State retained (if needed)

4. Power switch ON

5. De-isolation

⸻

Real-World SoC Usage

• CPU core sleep mode

• GPU power islands

• Peripheral shutdown blocks

⸻

Timing-Safe Power-Up Sequence (UPF)

This sequence avoids X-propagation, crowbar current, and timing violations during wake-up.

🔌 Power-Up Order (Recommended)

1️⃣ Keep Isolation ON

• Prevents unknown values from propagating

• Outputs are clamped to a known value (0 or 1)

set_isolation ISO_CORE -domain PD_CORE -clamp_value 0

2️⃣ Enable Power Switch (Ramp-Up)

• Gradual power ramp avoids IR-drop & inrush current

• Controlled by PS_EN

PS_EN = 1

⏱ Wait until VDD reaches stable level

3️⃣ Wait for Power Good (PG)

• Power must be stable before logic wakes up

• Implemented via analog or digital PG signal

wait (PWR_GOOD == 1);

4️⃣ Restore Retention Registers

• Restores saved state

• Done before clocks are released

set_retention_control RET_CORE -restore_signal RET_RESTORE

5️⃣ Release Reset

• Reset ensures known startup state

• Must occur after power + retention restore

RESET_N = 1;

6️⃣ Enable Clock

• Clock last to avoid spurious switching

• Prevents metastability

CLK_EN = 1;

7️⃣ Disable Isolation

• Domain now fully functional

set_isolation_control ISO_CORE -isolation_signal ISO_EN -deassert

⸻

📌 Golden Rule (Interview Favorite)

Isolation ON → Power ON → Power Good → Retention Restore → Reset Release → Clock ON → Isolation OFF

⸻

⚠️ What Happens If Sequence Is Wrong?

Mistake Result

Isolation OFF before power X-propagation

Clock ON before power Short-circuit current

Reset before power good Unknown state

No PG wait Timing failures

⸻

UPF Interview Questions & Answers

⸻

Q1. What is a power switch in UPF?

Ans: A power switch models header/footer transistors used to connect or disconnect power to a domain for leakage reduction.

⸻

Q2. Why is isolation required during power-up?

Ans: To prevent unknown (X) values from propagating from powered-off domains into active logic.

⸻

Q3. What is Power-Good (PG) signal?

Ans: A signal indicating that the supply voltage has reached a stable, safe operating level.

⸻

Q4. Difference between isolation and retention?

Isolation Retention

Protects outputs Preserves internal state

Mandatory Optional

Active when power OFF Active before power OFF

⸻

Q5. Why clocks are enabled last?

Ans: To prevent spurious switching and timing violations during unstable power.

⸻

Q6. What is inrush current and how do you avoid it?

Ans: Sudden current surge during power-up; avoided using staggered power switches or ramp-controlled enable.

⸻

Q7. Header vs Footer power switch?

Header Footer

PMOS NMOS

Low noise Area efficient

Near VDD Near GND

⸻

Q8. What happens if isolation is forgotten in UPF?

Ans: Functional simulation may pass, but gate-level simulation shows X-propagation and silicon failure.

⸻

Q9. Can a power-gated domain be clocked?

Ans: No. Clock must be gated OFF before power OFF and enabled only after power-up stabilization.

⸻

Q10. What checks ensure timing-safe power-up?

Ans:

• Power-aware STA

• UPF consistency checks

• PG signal timing validation

• Isolation/retention sequencing verification

⸻

“A timing-safe power-up ensures isolation first, stable power next, state restore, then clocks—never the other way around.”

UPF : Details on Level Shifter

UPF Quiz : On Power Switch

UPF Quiz : Level Shifter

RTL DIGITAL DESIGN

Apr 29, 2026

Table of Contents

CORDIC Implementation

Jan 19, 2026

C/C++ MCQ - Check your skill set

C / C++ Interview MCQ Test

C/CPP Interview Questions

Huffman Decoder

Decoder: Huffman Coding 📟

Jan 7, 2026

UPF : Power Switch