Verilog Code for Round Robin Algorithm

Round Robin algorithm details :
Round Robin algorithm Verilog code :

What is Round Robin algorithm ?

Round-robin (RR) is one of the algorithms employed by process and network schedulers in computing.As the term is generally used, time slices (also known as time quanta) are assigned to each process in equal portions and in circular order, handling all processes without priority (also known as cyclic executive). Round-robin scheduling is simple, easy to implement, and starvation-free. Round-robin scheduling can also be applied to other scheduling problems, such as data packet scheduling in computer networks. It is an operating system concept.

Below is the diagram.




In the real situation, we can have a modified version of round robin.
Below feature can be include while designing a arbiter using round robin.

1. If there are no requests,  which ever device/master send request, access will be given in next clock cycle.
2. For some master, priority can be set. 
3. Programmable delay to get the access if request is present. 

Below is the block diagram for round robin algorithm with 4 request and 4 grant.

Counter will be controlled by a state machine.

Verilog Code for Round Robin Algorithm : 

Below are the simulation results : 

In the same way, request/grant can be increased to n number.

Ref - https://en.wikipedia.org/wiki/Round-robin_scheduling

Table of Contents

Verilog code square root of a number

Verilog code to calculate the square root of a number ->

------------------Start of Verilog Code --------------------

`timescale 1ns/100ps

module square_root (
  input [31:0] num,
  output reg[31:0] sqr_root,
  output reg sqr_root_integer
 
  );
 
  integer temp;
  reg [31:0] i;
 
  always @(*) begin
   sqr_root = 'b0;
   sqr_root_integer = 1'b0;
   for (i = 0 ; i < (num/2) ; i = i+1 ) begin
      temp = i*i ;
     if (temp  == num) begin
       sqr_root_integer = 1 ;
       sqr_root = i ;
     end
   end
 end
endmodule

module tb;
  reg [31:0] num_in=0;
  reg clk =0;
  wire integer sqrr;
  wire valid;

  always #1 clk = ~clk;
 
  always @(posedge clk) begin
    num_in = num_in +1 ;
  end
 
  square_root DUT (
  .num(num_in),
  .sqr_root_integer(valid),
  .sqr_root(sqrr)
  );
 
  always@(sqrr)
    if(valid)
    $display("Square root of number %d is %d ", num_in , sqrr);

endmodule

-------------------  End of Code -------------------

Simulation result -> 

Thanks for reading my Blog. 

Table of Contents

Parameterized Modules in Verilog

How to pass parameter in verilog design from the top module ?

There are different method to do that , when a module is instantiate with different usage, probably width is one of the parameter which may not be same for all instantiation. For example, There is a FIFO design in which depth of the FIFO is parameterized mean FIFO depth can be set from top module. In below design , we see how to do that.

module fifo (
 parameter DEPTH = 10
)
(
input addr[ ] ,
input data [] ,
....
...
...
);

endmodule


Now we want to use this module in design A.

module A (  input  A ,
                   input B
);

// While instantiating the module, parameter can also be passed to fifo module.
fifo  #( .DEPTH(16) ) inst_fifo
(
.addr(),
.data(),
...
...
)

endmodule

in fifo #( .DEPTH(16)) inst_fifo , we can use parameter also.

fifo  #(.DEPTH(FIFO1_DEPTH)) inst_fifo ..

There are different ways to pass the parameter from top module.

Above parameter can be pass to module in this way also.

fifo  #(FIFO1_DEPTH) inst_fifo ..

In this case , if there are more than 1 parameter then order should be followed.

If a module has localparam , then it can not be override.

We can override the default values, either using defparam or by passing a new set of parameters during instantiation. We call this parameter overriding.

A parameter is defined by Verilog as a constant value declared within the module structure. The value can be used to define a set of attributes for the module which can characterize its behavior as well as its physical representation.

Defined inside a module.
Local scope.
Maybe overridden at instantiation time.
If multiple parameters are defined, they must be overridden in the order they were defined. If an overriding value is not specified, the default parameter declaration values are used.

Formal Definition

Parameters are constants typically used to specify the width of variables and time delays.
Simplified Syntax

parameter identifier = constant_expression ,

identifier = constant_expression ;

defparam hierarchical_path = constant_expression ;

This syntax is specified in the IEEE Standard (1800-2009, for example).

defparam is set during compilation time. 

Table of Contents

Verilog Code for Gray to Binary Code Converter

Block diagram for Gray to Binary Converter ->

Verilog code for Gray to Binary converter.

//-----------------------------------------------------------------------------
// Title       : Gray_to_Binary
// Design      : verilog upload
// Author      : Rahul Jain
//-----------------------------------------------------------------------------
//
// File        : Gray to Binary Code Converter 

module Gray_to_Binary ( din ,dout );

output [3:0] dout ;

input [3:0] din ;

assign dout[3] = din[3];
assign dout[2] = din[3]^din[2];
assign dout[1] = din[3]^din[2]^din[1];
assign dout[0] = din[3]^din[2]^din[1]^din[0];

endmodule

Gray to Binary Table for 4-bit.

Below is the simulation result using modelsim. 

Thanks for reading my Blog.

Table of Contents

Asynchronous FIFO with Programmable Depth

Asynchronous FIFO Design
Asynchronous FIFO Verilog Code
Asynchronous FIFO with block diagram and verilog Code.

This code is written in Verilog 2001.


Here is the block diagram for Asynchronous FIFO.

Verilog Code for Async FIFO

TestBench for Asynchronous FIFO 

Waveform Snapshot -:


Table of Contents

The Future of Semiconductor

Everyone in semiconductor industry is wondering  ,where semiconductor industry will go in next 5 years or so .. what are the career opportunities and scope in future at fresher level as well as experience level ?

We heard a lot of top semiconductor companies are doing layoff , they are going in loss and shutting down their units in all over the world.... but the good news is ,there are opportunities in semiconductor market to grow up.

I think everyone in VLSI must have heard about the Moore's law , if not then you can see at
http://en.wikipedia.org/wiki/Moore's_law

From Wikipedia -

Moore's law is the observation that, over the history of computing hardware, the number of transistors on integrated circuits doubles approximately every two years.

My wild guess is , the future product will now more focus on power saving logic , and it will going to explore more on physical level. Instead of reducing the size of transistor, people will think more to save power at transistor level.

All power consumption happen at transistor level only, if you move in that area, this might be a turning point of your career. Low-Power Design will be more preferable in market.

Back to the topic , in last 50 years , semiconductor industry have been all about the manifestation of Moore's law with respect to scal of integrated circuit. but as a consumer , what are the thing we would like to see in a electronics device .... first thing we look for is the cost and then we look for the features. But now it's close to saturation and we will not see much cost difference going forward as we saw in last 20 years .. where Nokia mobile phone comes around 15K INR and now same model you can get it in 2K INR ... its a huge difference. 

The chart below, published by IBS about 3 years ago, shows the diminishing benefit of cost reduction from dimensional scaling. In fact, the chart indicates that the 20nm node might be associated with higher cost than the previous node.

The following (somewhat busy) slide from IBM summarizes things clearly saying: "Net: neither per wafer nor per gate showing historical cost reduction trends"

With increasing cost in capitals, process, R&D , design and manufacturing, it is really impossible to provide more cheap device with high features loaded.

There is one more reason the sharp increase of costs with scaling , in previous days, moving from one node (one technology like 40nm ) to other node , there were always cost associated with but as comparative , it was small.

What's coming in future ??

Think carefully and tell , what is the future of semiconductor  ??  Design guys will get the design for next 5 or 8 years and once designs are there verification guys will also get the work .. for next 5 or 8 years atleast but then what will happen ?  Will all design , verification , P&R guys sits ideal and waiting for new technology  ?

There are saturation in all places , markets cracks and start from begin. But in semiconductor , there is no start from begin , people will have to think more deep and will have to come up with innovative ideas which will help to keep semiconductor industry moving.


People who are thinking to make career in this field , should think again. In 1995 , there were not many guys working in semiconductor , but from 2006/7/8 , many guys have started working in semiconductor domain .. after 5 years there will be many guys having 10+ years of exp ... what will be the scope for freshers that time ??

So My question is still there .... What coming next ???

I think 28nm will be in market for next 3-5 years because 28nm TSMC is very good technology and full fill the designers dream to get their block working at high frequency without any timing issue .. but there are always limitation :) .

20nm,14nm, 10nm, 7nm are also an upcoming technology, one having interest can explore more on that.

If you like the blog... Put your comments here :)
Also write your views about the future of Semiconductor.

A few example of Verilog Code 

1. Pattern Detection 2. Gray to Binary code 3. FIR Filter 4. Round Robin Algorithm 5. LED converter 6. Binary to Gray 7. Synchronous FIFO

source - 

http://www.eetimes.com/author.asp?section_id=36&doc_id=1286363

Other useful links -
How To debug a simulation 
Refreshing your brain with Verilog 
Digital Design of Hybrid Memory Cube
Correct way of  Digital design RTL Coding
Clock Gating Circuits
Digital Design Interview Question
Knowledge on Verification

Table of Contents

Simulator Execution for Blocking and non-blocking statement 

VHDL operator

VHDL Operators

   Highest precedence first,
   left to right within same precedence group,
   use parenthesis to control order.
   Unary operators take an operand on the right.
   "result same" means the result is the same as the right operand.
   Binary operators take an operand on the left and right.
   "result same" means the result is the same as the left operand.

**   exponentiation,  numeric ** integer,  result numeric
abs  absolute value,  abs numeric,  result numeric
not  complement,      not logic or boolean,  result same

*    multiplication,  numeric * numeric,  result numeric
/    division,        numeric / numeric,  result numeric
mod  modulo,          integer mod integer,  result integer
rem  remainder,       integer rem integer,  result integer

+    unary plus,      + numeric,  result numeric
-    unary minus,     - numeric,  result numeric

+    addition,        numeric + numeric,  result numeric
-    subtraction,     numeric - numeric,  result numeric
&    concatenation,   array or element & array or element,
                        result array

sll  shift left logical,     logical array sll integer,  result same
srl  shift right logical,    logical array srl integer,  result same
sla  shift left arithmetic,  logical array sla integer,  result same
sra  shift right arithmetic, logical array sra integer,  result same
rol  rotate left,            logical array rol integer,  result same
ror  rotate right,           logical array ror integer,  result same

=    test for equality, result is boolean
/=   test for inequality, result is boolean
<    test for less than, result is boolean
<=   test for less than or equal, result is boolean
>    test for greater than, result is boolean
>=   test for greater than or equal, result is boolean

and  logical and,                logical array or boolean,  result is same
or   logical or,                 logical array or boolean,  result is same
nand logical complement of and,  logical array or boolean,  result is same
nor  logical complement of or,   logical array or boolean,  result is same
xor  logical exclusive or,       logical array or boolean,  result is same
xnor logical complement of exclusive or,  logical array or boolean,  result is same

Table of Contents

Type of Adders with Verilog Code

Addition on 2 -bit  ->

d_out[1:0] =  a_in + b_in ;

Half Adder ->

Full Adder -->

Verilog Code ->

Half Adder -> 

module half_adder(a,b,sum,carry);

input a,b;

output sum, carry;

wire sum, carry;

assign sum = a^b; // sum bit

assign carry = (a&amp;b) ;

endmodule

Types of Adders :

1. Ripple Carry Adder 
2. Carry Lookahead Adder
3. RCLA (Ripple block carry lookahead adder)
4. BCLA (Binary carry lookahead adder)
5. conditional sum adder 
6. carry select adder 
7. carry skip adder 

    8.Parallel prefix adder -

• Ladner-Fischer adder
• Kogge-Stone adder
• Brent-Kung adder
• Han-Carlson adder

Ripple Carry Adder -> 

The most straightforward implementation of a final stage adder for two n-bit operands is a ripple carry adder, which requires n full adders (FAs). The carry-out of the ith FA is connected to the carry-in of the (i+1)th FA. Figure 1 shows a ripple carry adder for n-bit operands, producing n-bit sum outputs and a carry out. 

Verilog Code for Ripple carry Adder - 

-------------------------------------------------------------------- VERILOG CODE --------------------------------

module ripple_carry_adder ( 

 input [n-1:0] A_in,

 input [n-1:0] B_in,

 output [n-1:0] Sum,

 output Cn 

);

parameter n =10;

full_adder i_full_adder_0 ( .A(A_in[0] , .B(B_in[0], .sum(sum[0]) , .cin(1'b0), .cout(carry[0]) );

genvar c;
generate
for(c=1 ; c < n ; c = c +1) begin

  full_adder i_full_adder[c] ( .A(A_in[c]),
  .B(B_in[c]),
  .sum(sum[c]),
  .cin(carry[c-1]) ,
  .cout(carry[c])
  );
end

endgenerate

endmodule
-------------------------------------------------------------------- VERILOG CODE End -------------------------

Carry Lookahead Adder

 ---- Ref ---
 http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html#fsa_pfx

Table of Contents

Verilog Code for the counting number of 1's and 0's

Here is the verilog code for counting number of 1's and number of 0's in parallel data. since data is continuously changing on every clock cycle,  counting has to be done using parallel hardware.

Below is the code with testbench and simulation result :-

Does anyone know what will be the hardware synthesis tool will make ?

Is it going to be encoder , or  multiple adders or full of mux ??

---------------------------- Verilog Code ------------------

module count1n0 (
input clk,
input rstn,
input [9:0] data,
output reg [3:0] num_of_one,
output reg [3:0] num_of_zero
);

 

 always @(*) begin
      num_of_one  = 4'b0;
      num_of_zero = 4'b0;

    if(!data[0])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one + 1 ;

    if(!data[1])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[2])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[3])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[4])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[5])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[6])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[7])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[8])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[9])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

  end

endmodule
------------------------------------------------------

------------------- Verilog Testbench ----------------

module tb;

reg clk;
reg rstn;
reg [9:0] count;
wire [3:0] one;
wire [3:0] zero;

initial begin
clk =0;
rstn =0;
count =0;
end

initial begin
#100;
rstn = 1 ;
#1000;
$finish;
end

initial $monitor("data = %b, num of zero = %d, num_of_one = %d ", count , zero, one);

always @(negedge clk) begin
count = count + 1297;
end

always #5 clk = ~clk ;

count1n0 dut (
.clk(clk),
.rstn(rstn),
.data(count),
.num_of_one(one),
.num_of_zero(zero)
);

initial begin
 $recordfile("test.trn");
 $recordvars();
end

endmodule

----------------------------------------------------

-------------------Simulation Result - -------------

data = 0000000000, num of zero = 10, num_of_one =  0 

data = 0100010001, num of zero =  7, num_of_one =  3 

data = 1000100010, num of zero =  7, num_of_one =  3 

data = 1100110011, num of zero =  4, num_of_one =  6 

data = 0001000100, num of zero =  8, num_of_one =  2 

data = 0101010101, num of zero =  5, num_of_one =  5 

data = 1001100110, num of zero =  5, num_of_one =  5 

data = 1101110111, num of zero =  2, num_of_one =  8 

data = 0010001000, num of zero =  8, num_of_one =  2 

data = 0110011001, num of zero =  5, num_of_one =  5 

data = 1010101010, num of zero =  5, num_of_one =  5 

data = 1110111011, num of zero =  2, num_of_one =  8 

data = 0011001100, num of zero =  6, num_of_one =  4 

data = 0111011101, num of zero =  3, num_of_one =  7 

data = 1011101110, num of zero =  3, num_of_one =  7 

data = 1111111111, num of zero =  0, num_of_one = 10 

data = 0100010000, num of zero =  8, num_of_one =  2 

data = 1000100001, num of zero =  7, num_of_one =  3 

data = 1100110010, num of zero =  5, num_of_one =  5 

data = 0001000011, num of zero =  7, num_of_one =  3 

data = 0101010100, num of zero =  6, num_of_one =  4 

data = 1001100101, num of zero =  5, num_of_one =  5 

data = 1101110110, num of zero =  3, num_of_one =  7 

data = 0010000111, num of zero =  6, num_of_one =  4 

data = 0110011000, num of zero =  6, num_of_one =  4 

data = 1010101001, num of zero =  5, num_of_one =  5 

data = 1110111010, num of zero =  3, num_of_one =  7 

data = 0011001011, num of zero =  5, num_of_one =  5 

data = 0111011100, num of zero =  4, num_of_one =  6 

data = 1011101101, num of zero =  3, num_of_one =  7 

data = 1111111110, num of zero =  1, num_of_one =  9 

data = 0100001111, num of zero =  5, num_of_one =  5 

data = 1000100000, num of zero =  8, num_of_one =  2 

data = 1100110001, num of zero =  5, num_of_one =  5 

data = 0001000010, num of zero =  8, num_of_one =  2 

data = 0101010011, num of zero =  5, num_of_one =  5 

data = 1001100100, num of zero =  6, num_of_one =  4 

data = 1101110101, num of zero =  3, num_of_one =  7 

data = 0010000110, num of zero =  7, num_of_one =  3 

data = 0110010111, num of zero =  4, num_of_one =  6 

data = 1010101000, num of zero =  6, num_of_one =  4 

data = 1110111001, num of zero =  3, num_of_one =  7 

data = 0011001010, num of zero =  6, num_of_one =  4 

data = 0111011011, num of zero =  3, num_of_one =  7 

data = 1011101100, num of zero =  4, num_of_one =  6 

data = 1111111101, num of zero =  1, num_of_one =  9 

data = 0100001110, num of zero =  6, num_of_one =  4 

data = 1000011111, num of zero =  4, num_of_one =  6 

data = 1100110000, num of zero =  6, num_of_one =  4 

data = 0001000001, num of zero =  8, num_of_one =  2 

data = 0101010010, num of zero =  6, num_of_one =  4 

data = 1001100011, num of zero =  5, num_of_one =  5 

data = 1101110100, num of zero =  4, num_of_one =  6 

--------------------------------------------------------------

Thanks for visiting my blog. 

Table of Contents

Running Disparity

Disparity 

In order to create a DC-balanced data stream, the concept of disparity is employed to balance the number of 0s and 1s. 

The disparity of a block is calculated by the number of 1s minus the number of 0s. The value of a block that has a zero disparity is called disparity neutral. If both the 4-bit and 6-bit blocks are disparity neutral, a combined 10-bit encoded data will be disparity neutral as well. This will create a perfect DC-balanced code. 

However, this is not possible. Because only 6 out of the 16 possible values of the 4-bit block are disparity neutral, they are not enough for encoding the 8 values of the 3-bit block. 

Likewise, only 20 values of the 6-bit block are disparity neutral and they are not enough for encoding the 32 values of the 5-bit block. Because both the 4-bit and 6-bit blocks have an even number of bits, the disparity is not possible to be +1 or -1. Therefore, the values with a disparity of +2 and -2 are also used in the 8b/10b coding scheme. 

Table 1 and Table 2 are the values that are used for the 3-bit to 4-bit encoding and the 5-bit to 6-bit encoding respectively. Concatenating the 4-bit and 6-bit blocks together generates the 10-bit encoded value. Note that some of the encoded values in Table 1 and Table 2 have two possible values, one with a disparity value of +2 and the other with a disparity value of -2. The 8b/10b coding scheme was designed to combine the values of the 4-bit and 6-bit blocks perfectly so that the worst case disparity value of the 10-bit code group will be at most +2 or -2. 

For H G F E D C B A Dx.y a b c d e i f g h j MSB LSB LSB MSB LSB MSB 8b 10b or Kx.y code group 8b/10b Encoder/Decoder 3 example, the 4-bit encoded values with disparity value+2 will not be combined with the 6-bit encoded values with disparity value +2 because this will create a 10-bit value with disparity value +4.

In General , What is running disparity ?
Here is the definition -
Running disparity is the difference between the number of logic 1 bits and logic 0 bits between the start of a data sequence and a particular instant in time during its transmission. The RD for a character is the difference between the number of 1 bits and 0 bits in that character. If there are more 1 bits than 0 bits, the RD is defined as positive. If there are fewer 1 bits than 0 bits, the RD is defined as negative. If the number of 1 bits and 0 bits is the same, the RD is defined as neutral or zero.

As it is said, Running disparity is useful in DC balancing. After encoding 8-bit into 10-bits, few words still have more 1's than 0's or more 0's than 1's. DC balancing can be adjusted based on the running disparity.


So the next question is , How to calculate the running disparity ?
Answer is ,find out the number of 1's and number of 0's in the parallel data and based on the comparison , running disparity can be calculated.

Next question is , How to check the DC balance ?
Answer is , DC balancing is check the number of 1's and 0's in the data stream for a period of time , difference between number of 1's and 0's should not be large, if it is large , it means the encoding is not correctly implemented.

Please share your views or comments if you have any.
Thanks for reading my blog, have a nice day.

Table of Contents

Verilog Code for FIR Filter

FIR filters are is widely used in different applications such as biomedical, communication and control due to its easily implementation, stability and best performance. Its simplicity makes it attractive for many applications where it is need to minimize computational requirements.

Below is the code for FIR Filter , Any comments/doubts are welcome.

Please contact me if you want a soft copy of the module.

Block diagram :

F is the flopped stage and C1/C2/C3/C4/C5  are the coefficient. One bug adder will required to add all the feedback.

Below is the verilog code for FIR filter with test bench.
-----------

module fir_filter (  a, b, clk, rstn) ;

input signed [31:0] a;
output signed [31:0] b;
input clk;
input rstn;


parameter avg = 20;
parameter  c1 = avg*(8'h1) ;
parameter  c2 = avg*(8'h1) ;
parameter  c3 = avg*(8'h1) ;
parameter  c4 = avg*(8'h1) ;
parameter  c5 = avg*(8'h1) ;


reg signed [31:0] f1 ;
reg signed [31:0] f2 ;
reg signed [31:0] f3 ;
reg signed [31:0] f4 ;
reg signed [31:0] f5 ;


always @(posedge clk or negedge rstn) begin
  if(!rstn)  begin
    f1 <= 32'b0;
    f2 <= 32'b0;
    f3 <= 32'b0;
    f4 <= 32'b0;
    f5 <= 32'b0;
  end
  else begin
    f1 <= a;
    f2 <= f1;
    f3 <= f2;
    f4 <= f3;
    f5 <= f4;
  end
end


assign b = (f1*c1 + f2*c2 + f3*c3 + f4*c4 + f5*c5)/(5*avg) ;


endmodule

module tb_fir;

reg [31:0] in_signal;
reg clk =0;
reg rstn =0;
reg en =0;
wire [31:0] out_signal;

always #5 clk = ~clk;

integer cnt=0;

always @(clk) cnt = cnt +1 ;

always @(*) begin
   if(en ==1 && cnt[2:0] == 3'b111) begin
   #1;
  in_signal = cnt[7:0];
  end
  end

fir_filter dut (
.a(in_signal),
.b(out_signal),
.clk(clk),
.rstn(rstn));

initial begin
  rstn =0 ;
  #100;
  rstn = 1;
  en =1;
  #10000 ;
  $finish;
end

initial
 $monitor("Input signal = %d , out_signal = %d", in_signal, out_signal);

initial begin
  $recordfile("test.trn");
  $recordvars();
  end

endmodule

------------------------- verilog code end -------------------- 

Downloads the verilog file here. 

fir_filter.v

Low Power Design Technique : Tutorials

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Here are some low power technique used during RTL .

There are 3 main components for power calculation.

1. Dynamic Power
2. Static Power
3. Short Circuit Power 

Dynamic power 

Dynamic power of a chip can be reduced by reducing the number of switching from 1's to 0's and vice versa, this is design change and will required some of the best practice to write the HDL code. Few of them are listed below.

• Writing RTL for low power design

Static power 

Static power can be controlled by below techniques.

Multi voltage in design or it is called voltage island : 

multi voltage design in vlsi :

For Multi VDD See the UPF example , how the UPF is getting define for multi voltage design. Below is one of the simple example. Any communication from voltage1 to voltage2 will have to go through the level shifter to avoid any timing issues. 

How to insert Lever shifter for Voltage cross domain -> See UPF Example
Reducing voltage will reduce the power consumption but it will also reduce the performance of the block , it means if a block is expected to run at high frequency, there could be timing issues if using low voltage. Remember with higher voltage , setup time will be less. This is effective in SoC where a block is not expected to run at higher frequency. 

Synthesis setup would be different for multi voltage design , 1st UPF should be align with the voltage island. Level shifters libraries has to include in synthesis setup.

DVFS (dynamic voltage frequency scaling)

Dynamic voltage and frequency scaling (DVFS) is a technique that aims at reducing the dynamic power consumption by dynamically adjusting voltage and frequency of a CPU. This technique exploits the fact that CPUs have discrete frequency and voltage settings as previously described.

DVFS techniques provide effective power saving by reducing the voltage on the fly based on the performance requirements , it also reduce the operating frequency. This is the only techniques which is highly effective on dynamic and static power saving. Reducing frequency will reduce the dynamic power where as reducing voltage will reduce the static power. 

DVFS Example:

Implementation of  Dynamic Voltage Frequency Scaling : 

In the implementation stage , DVFS is done by using a combination of MSV and MMMC ( multi-mode/multi-corner) techniques. 

Multi Voltage Threshold

Multi Vth  is using multi voltage threshold level in the design , they are known as LVT/SVT/HVT cells and there utilization is depends on the timing requirement. LVT is faster cell but they have more leakage hence static power consumption will be more. 

A quick info on LVT/HVT cells.

Power gating Technique

(power shut off) -> This will require UPF to implement power switches in the design. We use power switch where some part of the design is not required to be active all the time.

Physical Implementation of Power Gating :

Synthesis uses the power switches according to the definition in UPF ( power swtich must be define in UPF , it describe the control signal and other details which is required for synthesis tool to implement it.  The main task during synthesis is adding isolation cells, retention cells and always on cells define in UPF. The conneciton of power switch cells to the power control module happens during the physical implementation flow, when physical implementation information is available to the tool. 

Clock Gating Circuit 

Most of the dynamic power in design is consumed by clock , clock gating is the effective way to reduce the power consumption. There are options available in synthesis tool where you can enable the auto clock gating option , Tool will insert the clock gating at most of the places.

Visit here to see more detail information on Low Power Design Techniques.

Table of Contents


------------

multi voltage design in vlsi

------------

SPI Protocol

APTITUDE QUESTIONS

Many more yet to come, Stay Tuned.

Sample Question :


1.
Tanya is older than Eric.
Cliff is older than Tanya.
Eric is older than Cliff.
If the first two statements are true, the third statement is

A. true
B. false
C. uncertain

2.

Which cells are placed in Soft blockages?No cells
Any cells
Only sequential cells
Only Buffers and Inverters



3.
Metal layer ____ has Maximum resistance?1
2
3
4


4.
What does chip utilization depend on?Only on standard cells
Only on macros
Standard cells and macros both
Standard cells, macros and IO pads

5.
Leakage power is inversely proportional to _____________.
Frequency
Load Capacitance
Supply voltage
Threshold Voltage

6.
What does Prerouting mean?
Routing of clock nets
Routing of signal nets
Routing of IO nets
Routing of PG nets

7.
Utilisation of the chip after placement optimisation will _____________.
Be Constant
Decrease
Increase
None of the above

8.

What is the purpose of CTS?
Minimum Slack
Minimum Skew
Minimum EM
Minimum IR Drop

9.
Which cells would you place in the critical path for a better timing?
LVT
HVT
RVT
SVT


10.
Which of the following is a correct boolean expression ?a) A + A = A b) A+AB = B c) AB' + B'A = A+B d) None

Ans = a


11.
How many 2:1 mux can be used to implement 3:8 decoder ?
a) 5 b) 6 c) 8 d) 7

VLSI Industry Updates

VLSI News Update :-

12 Dec 2016

IoT and Automotive to Drive IC Market Growth Through 2020

Ref_Link
11/14/2016 04:10 PM EST
TOKYO — Within the last 24 hours, two big players — Samsung and Siemens — announced M&A deals in the automotive field. Samsung will pay $8 billion for the U.S. car technology group Harman, while Siemens agreed to acquire Mentor Graphics, an EDA company, in $4.5 billion deal.
Ref_Link


11/14/2016 00:01 AM EST
7nm SRAMs, 10nm SoC at ISSCC
TSMC nudges out Samsung in small SRAMs
Ref_Link


Top News for the Day - Technology & Industry 1. Google buys HTC talent for $1.1 billion to spur devices push Read more at: https://lnkd.in/fmqjGD5 2. Deep learning is the money tree for IT companies Read more at: https://lnkd.in/f4Mq6Za 3. NASSCOM signs agreement with local Chinese government to push for AI Read more at: https://lnkd.in/fR2yq73 4. Companies get ready for 5G future Read more at: https://lnkd.in/fveRZSR 5. Matrimony.com makes a quiet debut; lists at par against IPO price of Rs 985 - https://lnkd.in/fZFaUpw 6. WeChat is quietly developing its own augmented reality platform - https://lnkd.in/fnK44u7

Table of Contents

Implementation of Logical Questions

Coming soon with OOB questions and answer . stay tuned.

Please leave your comments if you want to add logical question or have any doubt.

Q1. Design a Lift controller. Below are the specification.

1. Life can move from flr-0 to flr-20.
2. There is only 1 lift.
3. Priority should be given if input given from inside of lift.

Prepare the document first, after that RTL coding in verilog.


Q2. Continue with Q1, there is one more life.  All specifications are same.
Design the controller efficiently.

Prepare the document first with analysis part. how many conditions will be there and what will be the decision.  Round robin/ Priority based arbitration can be used to resolve conflict.

Q3. Traffic light controller using verilog.
Specification -
Consider a controller for traffic light at the intersection of four roads. Consider R1, R2, R3 and R4 as four roads and PL as Pedestrian. The road has the following stages.
Green=10011, Yellow=01000,  Red=00100.

The pedestrian has following two states
Green=0000  ,Red=1111

First the road R1 is green and all other roads R2, R3 ,R4 and PL are red .After a some delay R1 is turn to yellow and then red the traffic signal on R2 is green. After a delay R2 is turn to yellow and then red the signal on R3 is green.Then R3 is changed to yellow and then red. Similarly R4 is turned green then yellow & then red. Pedestrian Light PL is green after a delay. Again R1 is turned to green & the routine will continue.

Q4.  Continuation from Q3 , with all specification in Q3,  each road having one sensor.  Sensor sense the traffic and it give output to traffic light mechanism if no vehicle cross it for a time period. Based on the input from sensor, traffic light can change the state.

Q5. Design a hardware to count the number of 1's and 0's in 40-bit data. Data is coming continuously.

Table of Contents

CDC - Real time implementation

Few CDC related Info -

Clock domain issue in real time
MTBF Info

Clock convergence
Guideline to Handle Multi clocks in Design - Everyone must go through it

Table of Contents

Verilog Code for modules

Below are the modules will be available soon with documents and Verilog code , Contact me if anyone interested to do the project work.

Page will update very soon , Stay tuned.

AHB Controller

Features :

AXI Controller

Features :

AXI Interconnect

Features ;

8b10encoder/decoder

Adders

ALU

FIR_FILTER

Binary_To_Gray_Conversion

Parity_Checker 

Table of Contents

Protocol

Here are the most used protocols in design , based on application.

List of protocol in VLSI :

Serial Protocol -
SPI Protocol
UART Protocol
I2C Protocol
Under Construction :-
I2S
I3C
Ethernet IP
PCIe
Fiber Channel
SATA
CAN
USB


Under Construction :-

Bus Protocol
AXI
AHB
AMBA
OCP
AVALON


Networking Protocol
SATA / SAS
PCIe
WIFI/WIMAX
Bluetooth
OSI Protocol
TCP Protocol
PPP - Point to Point Protocol
SFTP
HTTP
HTTPS
SSL
NTP
IMAP

Display
HDMI
Video Codec

Table of Contents