Addition on 2 -bit ->
d_out[1:0] = a_in + b_in ;
Half Adder ->
Full Adder -->
Verilog Code ->
Half Adder ->
module half_adder(a,b,sum,carry);
input a,b;
output sum, carry;
wire sum, carry;
assign sum = a^b; // sum bit
assign carry = (a&b) ;
endmodule
Types of Adders :
- Ripple Carry Adder
- Carry Lookahead Adder
- RCLA (Ripple block carry lookahead adder)
- BCLA (Binary carry lookahead adder)
- conditional sum adder
- carry select adder
- carry skip adder
- Ladner-Fischer adder
- Kogge-Stone adder
- Brent-Kung adder
- Han-Carlson adder
Ripple Carry Adder ->
The most straightforward implementation of a final stage adder for two n-bit operands is a ripple carry adder, which requires n full adders (FAs). The carry-out of the ith FA is connected to the carry-in of the (i+1)th FA. Figure 1 shows a ripple carry adder for n-bit operands, producing n-bit sum outputs and a carry out.
Verilog Code for Ripple carry Adder -
-------------------------------------------------------------------- VERILOG CODE --------------------------------
module ripple_carry_adder (
input [n-1:0] A_in,
input [n-1:0] B_in,
output [n-1:0] Sum,
output Cn
);
parameter n =10;
full_adder i_full_adder_0 ( .A(A_in[0] , .B(B_in[0], .sum(sum[0]) , .cin(1'b0), .cout(carry[0]) );
genvar c;
generate
for(c=1 ; c < n ; c = c +1) begin
full_adder i_full_adder[c] ( .A(A_in[c]),
.B(B_in[c]),
.sum(sum[c]),
.cin(carry[c-1]) ,
.cout(carry[c])
);
end
endgenerate
endmodule
-------------------------------------------------------------------- VERILOG CODE End -------------------------
Carry Lookahead Adder
---- Ref ---
http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html#fsa_pfx
