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May 15, 2014

RTL Techniques to make device a Low Power Device


In my last blog , I have explain about the low power technique which includes rtl modification , cell selection, using UPF file, power saving at physical level , etc . During RTL implementation, a good designer can save a significant amount of power.

As we all knows power loss in chip is due to static power and dynamic power. During RTL implementation, we can not do anything on static power but we can save dynamic power by reducing number of transitions at gates. Below are few bullet points.

Power Saving during RTL Implementation 

1. One should write RTL in such  way where transition should be minimum , for example

always@(posedge clk or negedge reset) begin
 if(reset)
    data_out <= 64'd0;
 else if (latch_en)
   data_out <= data_in;
 else
   data_out <= 64'd0 ;
end

Above code can be written as shown below -

always@(posedge clk or negedge reset) begin
 if(reset)
    data_out <= 64'd0;
 else if (latch_en)
   data_out <= data_in;
end

If there is no need to reset data_out when latch_en is not high , then there is no harm to leave previous data on data bus, this will save lot of transition and will result in saving power.

2.  Implement clock gating for the blocks which are not required in some power state or in functional mode.
Clock gating is important if design intention is low power , one using clock gating, should use proper clock gating cells. Enable/disable signal of clock gating should be synchronized with respective clock domain to avoid glitches.

3.  In a design, there may be lot of counters , big or small ... to save power , those counters should not be free running counters. Use start and stop condition and run those counters whenever required.
Counters should be taken care in micro-architecture document, start/stop condition will be depend on certain condition which should be met.

4. Sharing logic will also help in reducing power as well as effective gate count.
Logic may get optimized during synthesis as tool is now having intelligence to detect same kind of logic and optimized them. But this will open a small confusion window as tool may or may not optimized the logic. It is always advised to share logic at RTL stage itself.

5.  If design having big state machine then prefer to use gray coding or one hot coding , In binary coding , transition will be more and will consume more power.

When you are working on micro-architecture of design, and if you want to make design as low power design then you need to think carefully about the transition. sometimes it might be possible that transitions are not in big numbers but when you save small numbers transitions multiple places then it will result in saving good amount of power.

The only disadvantage is , hardware will be more as you need to implement more logic and consumption of your mind power will be more as you need to think out of box to implement the logic. But at the end you will be called "expert in Low Power Design" which will open a lot of opportunities for your career and your future.


Let me know if I am missing something here , I can add here and make this article more effective. 

Thanks for your time. 

Rahul Jain 

May 14, 2014

UPF Example


Below link is the UPF example, I have tried my best to put all things in one page to get better understanding.

You might have to adjust your display setting to view it properly.
























This diagram does not included the advanced command of UPF (new commands added in UPF2.0 ) , I will try to get those command in same figure .. Keep visiting my blog for updates.

Here are the some quizzes on UPF , plz do not forget to mention your score in comment :)
UPF  QUIZZES

My linked-in profile -
Linked-in (Rahul Jain)

Other useful links -
How To debug a simulation 
Refreshing your brain with Verilog 
Digital Design of Hybrid Memory Cube
Correct way of  Digital design RTL Coding
Clock Gating Circuits
Digital Design Interview Question
Knowledge on Verification


Simulator Execution for Blocking and non-blocking statement 

(UPF) Unified Power Format

VLSI Digital Design Interview Questions  

Unified Power Format (UPF) is the popular name of the Institute of Electrical and Electronics Engineers (IEEE) standard for specifying power intent in power optimization of electronic design automation. The IEEE 1801-2009 release of the standard was based on a donation from the Accellera organization.

How does it started ? 
A technical committee was formed by the Accellera organization, chaired by Stephen Bailey (Mentor Graphics). This group was met on Sep13,2006 and it submitted its first draft in Jan 2007. After that Version 1.0 was approved to be published on Feb 26,2007, Joe Daniel was technical editor. 

After publishing version 1.0, there were 2 other version published later , version 2.0 and version 2.1. 

Accellera UPF in 2007 (1.0)
IEEE 1801-2009 UPF (2.0)
IEEE 1801-2013 UPF (2.1) 

Q. What is UPF and how to use it in design ? 
UPF is Tcl based syntax and semantics and can be mixed with non-UPF Tcl commands. I will explain the usage of this file. 
This file defining the power management architecture of the design, and used in generating customized reports related to power intent of design.There are standard commands defined in UPF which tool understand and respond according to that. 

UPF Flow 



Below is a snapshot of UPF 1.0 version commands, all commands will have explanation. 




Power Doamin
This is not a command but a term used while explaining the commands.
A power domain is a collection of design elements that share a primary power and ground supply net. The
logic hierarchy level where a power domain is created is called the scope of the power domain. Any design
elements that belong to a power domain are said to be in the extent of that power domain.
Whenever a UPF object, such as a supply net or switch is created, it is always created in the scope of the
power domain.

UPF commands 

set_scope
It specify the current scope of UPF , syntax is
set_scope my_dut/design_a

set_design_top
It specify the top level design instance , this information is used only by simulation and verification tools.
Syntax -
set_design_top <design name>

create_supply_port
Syntax of this command is -
create_supply_port  port_name -domain <domain_name> -direction <in | out >

create_supply_net 
The create_supply_net command creates a supply net. The net is defined for the power domain, created in the logic hierarchy at the same scope as domain_name, and propagated through implicitly created ports and nets through the logic hierarchy as required.
Syntax -
create_supply_net <net_name> -domain <power_domain> -reuse  -resolve <unresolved | parallel | one hot>

Here -domain is power domain where you want to create net.
-reuse - (optional) extend net_name as a supply net within domain_name , new nets will not be created.
-resolve  - optional

connect_supply_net
This command used to connect supply_net to supply ports or/and supply pins.
Syntax -
connect_supply_net net_name  [-ports list] [-pins list]  [<-cells list |-domain domain_name>]  [<-rail_connection rail_type | -pg_type pg_type>]* [-vct vct_name]

-cells list A list of cells to use for -rail_connection or -pg_type.
-domain domain_name The domain to use for -rail_connection or -pg_type.
-rail_connection rail_type  (The rail type (for older libraries).)
-pg_type pg_type The power/ground pin type.
-vct vct_name A VCT defining how values are mapped from UPF to an HDL model or from the HDL model to UPF.

create_power_switch
It define a power switch in the power domain.
Syntax -
create_power_switch switch_name
-domain domain_name
-output_supply_port {port_name supply_net_name}
{-input_supply_port {port_name supply_net_name}}
{-control_port {port_name net_name}}
{-on_state {state_name input_supply_port {boolean_function}}}
[-on_partial_state {state_name input_supply_port {boolean_function}}]
[-ack_port {port_name net_name [{boolean_function}]}]
[-ack_delay {port_name delay}]
[-off_state {state_name {boolean_function}}]
[-error_state {state_name {boolean_function}}]


create_power_domain
It define the power supply distribution network, a power domain is logical grouping of one or more design elements.

Syntax -
create_power_domain domain_name [-elements list]  [-include_scope]  [-scope instance_name]
domain_name - new power domain, should be a simple name
-element <list> , list is specified to current scope , not influenced by -scope argument
if -include_scope is specified , the scope of domain is included in the extent of the domain.
-scope , it specifies the scope i.e. where the domain shall be created.
Example -
create_power_domain PD1 -elements {top/U1}
set_scope /top/U1
create_power_domain PD2

set_domain_supply_net
Set default power and ground supply net for a power domain.
Syntax -
set_domain_supply_net domain_name   -primary_power_net supply_net_name  -primary_ground_net supply_net_name

add_port_state
Specify the name and value for a supply port.
Syntax -
add_port_state port_name  {-state {name <nom | <min nom max> | off>}}

Example -
add_port_state VPP  -state {active_state 0.88 0.90 0.92}   -state {off_state off}

create_pst
Create a power state table with a specific ordering of supply nets.
Syntax -
create_pst table_name  -supplies list

A power state table is used for implementation — specifically for synthesis, analysis, and optimization. It
defines the legal combinations of states, i.e., those combinations of states that can exist at the same time
during operation of the design.

add_pst_state
Define the states of each of the supply nets for one possible state of the design.
Syntax -
add_pst_state state_name  -pst table_name  -state supply_states

Syntax example:
create_pst pt -supplies { N1 N2 DUT/T1/VDD1 }
add_pst_state s0 –pst pt –state { s08 s08 s0 }
add_pst_state s1 –pst pt –state { s08 s08 off }
add_pst_state s2 –pst pt –state { s08 s09 off }

set_retention
Defining the retention registers in design.
Syntax -
set_retention retention_name -domain domain_name  <-retention_power_net net_name | - retention_ground_net net_name | -retention_power_net net_name -retention_ground_net net_name>  [-elements list]

set_retention_control
It specify the control signals and assertions for retention cells.
Syntax -
set_retention_control retention_name -domain domain_name  -save_signal {{net_name <high | low | posedge | negedge>}}  -restore_signal {{net_name <high | low | posedge | negedge>}}
[-assert_r_mutex {{net_name <high | low | posedge | negedge>}}]
[-assert_s_mutex {{net_name <high | low | posedge | negedge>}}]
[-assert_rs_mutex {{net_name <high | low | posedge | negedge>}}]

set_isolation
Specify the elements in the domain to isolate using the specified strategy.
set_isolation isolation_name -domain domain_name  <-isolation_power_net net_name | -isolation_ground_net net_name |  -isolation_power_net net_name -isolation_ground_net net_name | -no_isolation>  [-elements list] [-clamp_value <0 | 1 | latch | Z>] [-applies_to <inputs | outputs | both>]

set_isolation_control
Specify the isolation control signals and assertions in specified strategy.
Syntax -
set_isolation_control isolation_name  -domain domain_name  -isolation_signal signal_name  [-isolation_sense <high | low>]  [-location <self | parent | sibling | fanout | automatic>]

set_level_shifter
Specify the level shifter in design.
Syntax -
set_level_shifter level_shifter_name  -domain domain_name  [-elements list] [-applies_to <inputs | outputs | both>]  [-threshold value] [-rule <low_to_high | high_to_low | both>]  [-location <self | parent | sibling | fanout | automatic>] [-no_shift]

map_retention_cell
Specify the retention cells used for retention registers.
Syntax -
map_retention_cell retention_name
-domain domain_name
[-elements list]
[-lib_cells list]
[-lib_cell_type lib_cell_type]
[-lib_model_name lib_cell_name {-port port_name net_name}]

map_isolation_cell
Syntax -
map_isolation_cell isolation_name  -domain domain_name [-elements list]  [-lib_cells list]  [-lib_cell_type lib_cell_type]  [-lib_model_name lib_model_name {-port {port_name net_name}}]

map_level_shifter_cell
Map a particular level shifter strategy to a library cell or range of library cells.
Syntax -
map_level_shifter_cell level_shifter_name  -domain domain_name  -lib_cells list [-elements list]

map_power_switch_cell
Specify which power switch cell is to be used for the corresponding switch instance.
map_power_switch switch_name  -domain domain_name  -lib_cells list

bind_checker
Inserts checker modules and binds them to design elements.
Syntax -
bind_checker instance_name  -module checker_name  -elements list  [-ports {{port_name net_name}}]

create_hdl2upf_vct
Define value conversion table that can be used in converting HDL logic values into net_state_type values.
Syntax -
create_hdl2upf_vct vct_name  -hdl_type {<vhdl | vlog | SV> [typename]}  -table {{from_value to_value}}

create_upf2hdl_vct
Define value conversion table that can be used in converting UPF supply_net_type.state(1:0) values into HDL logic values.
Syntax -
create_upf2hdl vct_name  -hdl_type {<vhdl | vlog | SV> [typename]}  -table {{from_value to_value}}

upf_version
Specify the version for the UPF file/syntax.
Syntax -
upf_version [string]

load_upf
Set the scope to the specified instance and execute the specified UPF commands.
Syntax -
load_upf upf_file_name  [-scope instance_name]  [-version string]

save_upf
Create a UPF file relative to the specified scope.
Syntax -
save_upf upf_file_name  [-scope instance_name]  [-version string]

----------------------------------------------------------------------------------------------------------

After UPF version 1.0, there was in need of enhancement to save power more precisely, then UPF 2.0 came in 2009. In UPF2.0, there were many new commands , below is a summary of UPF2.0 addition.
Red commands are the new addition in UPF 2.0. 



set_simstate_behavior
Specify the simulation simstate behavior for a model or library.
Syntax-
set_simstate_behavior <ENABLE | DISABLE>  [-lib name]  [-model model_list]  [-elements element_list] [-exclude_elements exclude_list]

set_port_attributes
It defines attributes on ports.
Syntax -
set_port_attributes   [-model name]
[-elements element_list]
[-exclude_elements element_exclude_list]
[-ports port_list]
[-exclude_ports port_exclude_list]
[-applies_to <inputs | outputs | both>]
[-attribute {name value}]*
[-clamp_value <0 | 1 | any | Z | latch | value>]
[-sink_off_clamp <0 | 1 | any | Z | latch | value>]
[-source_off_clamp <0 | 1 | any | Z | latch | value>]
[-driver_supply supply_set_ref]
[-receiver_supply supply_set_ref]
[-pg_type pg_type_value]
[-related_power_port supply_port_name]
[-related_ground_port supply_port_name]
[-related_bias_ports supply_port_name_list]
[-feedthrough]
[-unconnected]
[{-domains domain_list [-applies_to <inputs | outputs | both>]}]
[{-exclude_domains domain_list [-applies_to <inputs | outputs | both>]}]
[-repeater_supply supply_set_ref]
[-transitive [<TRUE | FALSE>]]

set_design_attributes
Apply attributes to models or instances
Syntax -
set_design_attributes  [-models model_list]  [-elements element_list]  [-exclude_elements exclude_list]  [-attribute {name value}]  [-is_leaf_cell [<TRUE | FALSE>]]  [-is_macro_cell [<TRUE | FALSE>]]

associate_supply_set
Associate a supply set with a power domain, power switch, or strategy supply set handle.
Syntax -
associate_supply_set supply_set_name
-handle supply_set_handle

set_retention_elements 
Create a named list of elements to be used in set_retention or map_retention_cell commands
Syntax -
set_retention_elements retention_list_name  -elements element_list
[-applies_to <required | not_optional | not_required | optional>]
[-exclude_elements exclude_list]
[-retention_purpose <required | optional>]
[-transitive [<TRUE | FALSE>]]
[-expand [<TRUE | FALSE>]]

use_interface_cell
Specify the functional model and a list of implementation targets for isolation and level-shifting.
Syntax -
use_interface_cell interface_implementation_name  -strategy list_of_isolation_level_shifter_strategies
-domain domain_name  -lib_cells lib_cell_list
[-port_map {{port net_ref}*}]
[-elements element_list]
[-exclude_elements exclude_list]
[-applies_to_clamp <0 | 1 | any | Z | latch | value>]
[-update_any <0 | 1 | known | Z | latch | value>]
[-force_function]
[-inverter_supply_set list]

create_logic_port
Define a logic port.
Syntax -
create_logic_port port_name  [-direction <in | out | inout>]

create_logic_net
Define a logic net.
Syntax -
create_logic_net <net_name>

connect_logic_net
Connect a logic net to logic ports.
Syntax -
 connect_logic_net net_name  -ports port_list  [-reconnect]

load_upf_protected
Load a UPF file in a protected environment that prevents corruption of existing variables.
Syntax -
load_upf_protected upf_file_name  [-hide_globals] [-scope instance_name_list]  [-version upf_version] [-params param_list]

load_simstate_behavior
Load the simstate behavior defaults for a library.
Syntax -
load_simstate_behavior lib_name  -file file_list

find_objects
Find logic hierarchy objects within a scope.

create_composite_domain
A composite power domain is a simple container for a set of power domains. Unlike a power domain, a

composite domain has no corresponding physical region on the silicon.

add_power_state
Define power state(s) of a power domain or supply set.
Syntax -
add_power_state object_name  [-supply | -domain]  [-state {state_name [-supply_expr {boolean_expression}]  [-logic_expr {boolean_expression}]  [-simstate simstate] [-legal | -illegal]}] [-complete]  [-update]

describe_state_transition
Describe a state transition’s legality.
Syntax -
describe_state_transition transition_name  -object object_name  [-from from_list -to to_list]
[-paired {{from_state to_state}}]  [-legal | -illegal]

Each command will need a detail explanation, I have tried to put more information in below post.

UPF Example 

Ref-
http://en.wikipedia.org/wiki/Unified_Power_Format
ftp://c-76-121-39-184.hsd1.wa.comcast.net/AiDisk_a1/WK/FP/PROJ/docs/IEEE/1801-2013.pdf

May 10, 2014

Verilog - System Task


$bitstoreal 
Convert bits into real number.
Syntax
wire [64:1]  abc;
real  num = $bitstoreal(abc);

$countdrivers
The $countdrivers system function is provided to count the number of drivers on a specified net so that bus contention can be identified.

Syntax -
$countdrivers(net, net_is_forced, number_of_01x_drivers, number_of_0_drivers, number_of_1_drivers, number_of_x_drivers);

This system function returns a 0 if there is no more than one driver on the net and returns a 1 otherwise (indicating contention).

net_is_forced returns a "1" if the net is forced and a "0" if the net is not forced
number_of_01x_drivers returns an integer representing the number of drivers that are in a 0, 1, or x state; this represents the total number of drivers on the net that are not forced
number_of_0_drivers returns an integer representing the number of drivers on the net that are in the "0" state
number_of_1_drivers returns an integer representing the number of drivers on the net that are in the "1" state
number_of_x_drivers returns an integer representing the number of drivers on the net that are in the "x" state

$display or $write
These are the main system task routines for displaying information.
Syntax -
$display (Q1,Q2,Q3....Qn );


The contents of string parameters are output literally except when certain escape sequences are inserted to display special characters or specify the display format for a subsequent expression.
It could be inserted in 3 different ways -
1. The special character \ indicates that the character to follow is a literal or non-printable character.
2. The special character % indicates that the next character should be interpreted as a format specification
3. The special character string %% indicates the display of the percent sign character %

\n is the newline character
\t is the tab character
\\ is the \ character
\" is the " character
\o is a character specified in octal digits
%% is the percent character

%h or %H display in hexadecimal format
%d or %D display in decimal format
%o or %O display in octal format
%b or %B display in binary format
%c or %C display in ASCII character format
%v or %V display net signal strength
%m or %M display hierarchical name
%s or %S display as a string
%t or %T display in current time format

%e or %E display `real' in an exponential format
%f or %F display `real' in a decimal format
%g or %G display `real' in exponential or decimal format, whichever format results in the shorter printed output

$strobe
Syntax -
Same as $display.  escape charc and all are same as used in $display.

The difference between $display and $strobe is , $strobe executed at the end of current simulation cycles , which means after all events executed then actual value will be displayed by $strobe.

$monitor
Syntax  - same as $display

The $monitor task provides the ability to monitor and display the values of any variables or expressions specified as parameters to the task.
When you invoke a $monitor task with one or more parameters, the simulator sets up a mechanism whereby each time a variable or an expression in the parameter list changes value–with the exception of the $time, $stime or $realtime system functions–the entire parameter list is displayed at the end of the time step as if reported by the $display task. If two or more parameters change value at the same time, however, only one display is produced that shows the new values.

Note that only one $monitor display list can be active at any one time; however, you can issue a new $monitor task with a new display list any number of times during simulation.

$monitoroff
$monitoron
The $monitoron and $monitoroff tasks control a monitor flag that enables and disables the monitoring, so that you can easily control when monitoring should occur. Use $monitoroff to turn off the flag and disable monitoring. Use $monitoron to turn on the flag so that monitoring is enabled and the most recent call to $monitor can resume its display. A call to $monitoron always produces a display immediately after it is invoked, regardless of whether a value change has taken place; this is used to establish the initial values at the beginning of a monitoring session. By default, the monitor flag is turned on at the beginning of simulation.


$fopen , $fclose , $fwrite, $fdisplay, $fmonitor, $fstrobe 
Each of the four formatted display tasks—$display, $write, $monitor, and $strobe—has a counterpart that writes to specific files as opposed to the log file and standard output. These counterpart tasks—$fdisplay, $fwrite, $fmonitor, and $fstrobe—accept the same type of parameters as the tasks they are based upon, with one exception: The first parameter must be a multichannel descriptor that indicates where to direct the file output.

integer filepp = $fopen("<file_for_writing>");
$fwrite(filepp, " same as $write" );
$fdisplay(filepp, "same as $display");
$fmonitor(filepp, "same as $monitor");
$fstrobe(filepp, "same as strobe" );
$fclose(filepp);



$finish
Syntax:
$finish;
$finish (n);
The $finish system task simply makes the simulator exit and pass control back to the host operating system. If a parameter expression is supplied to this task, then its value determines the diagnostic messages that are printed before the prompt is issued. If no parameter is supplied, then a value of 1 is taken as the default.

0 prints nothing
1 prints simulation time and location
2 prints simulation time, location, and statistics about the memory and CPU time used in simulation

$getpattern


$history
The $history system task prints out a list of all interactive commands that have been entered to a tool.


$input
Syntax - $input("<filename>");
The $input system task allows command input text to come from a named file instead of from the terminal. At the end of the command file the input is automatically switched back to the terminal.

$itor
converts integers to real values (for example, 123 becomes 123.0)

$rtoi
converts real values to integers by truncating the real value (for example, 123.45 becomes 123)

$key
$nokey
$key(“<filename>”);$key;$nokey;
A key file is created by a tool whenever interactive mode is entered for the first time. The key file contains all of the text that has been typed in from the standard input. The file also contains information about asynchronous interrupts.

The $nokey and $key system tasks are used to disable and re-enable output to the key file. An optional file name parameter for $key causes the old key file to be closed, a new file to be created, and output to be directed to the new file.

$list
Syntax -
$list;$list (<name>);

When invoked without a parameter, $list produces a listing of the module, task, function, or named block that is defined as the current scope setting. If an optional parameter is supplied, it must refer to a specific module, task, function or named block, in which case the specified object will be listed.

$log
$nolog
Syntax -
$log(“<filename>”);$log;$nolog;
Tools may create a log file that contains a copy of all the text that is printed to the standard output. The log file may also contain, at the beginning of the file, the host command that was used to run the tool.

The $nolog and $log system tasks are used to disable and re-enable output to the log file. The $nolog task disables output to the log file, while the $log task re-enables the output. An optional file name parameter for $log causes the old file to be closed, a new log file to be created, and output to be directed to the new log file.

$printtimescale
Syntax:

$printtimescale <hierarchical_name>;
When no argument is specified, $printtimescale displays the time unit and precision of the module that is the current scope (as set by $scope).

When an argument is specified, $printtimescale displays the time unit and precision of the module passed to it.

$readmemb
$readmemh
$readmemb("<filename>", <memname>);
$readmemb("<filename>", <memname>, <start_addr>);
$readmemb("<filename>", <memname>, <start_addr>, <finish_addr>);

$readmemh("<filename>", <memname>);$readmemh("<filename>", <memname>, <start_addr>);

$realtime , $time 
The $realtime system function returns a real number time that, like $time, is scaled to the time unit of the module that invoked it.
The $time and $realtime system functions return the current simulation time. The function $time returns a 64 bit value, scaled to the time unit of the module that invoked it. If the time value is a fraction of an integer, $time returns zero. The function $realtime returns a real number that is scaled to the time unit of the module that invoked it.

For example:
`timescale 10 ns / 1 ns
module test;
reg set;
parameter p = 1.55;
initial
begin
$monitor($realtime,,"set=",set);
#p set = 0;
#p set = 1;
end
endmodule
// The output from this example is as follows:
// 0 set=x
// 1.6 set=0

// 3.2 set=1


$realtobits
converts real values to integers by truncating the real value (for example, 123.45 becomes 123)

$reset
$reset_count
$reset_value
The $reset system task enables a tool to be reset to its “Time 0” state so that processing (e.g., simulation) can begin again.
The $reset_count system function keeps track of the number of times the tool is reset. The $reset_value system function returns the value specified by the reset_value parameter argument to the $reset system task. The $reset_value system function is used to communicate information from before a reset of a tool to the time 0 state to after the reset.
The following are some of the simulation methods that you can employ with this system task and these system functions:
• determine the force statements your design needs to operate correctly, reset the simulation time to 0, enter these force statements, and start to simulate again
• reset the simulation time to 0 and apply new stimuli
Verilog HDL LRM 260 • List of System Task and System Function Keywords
• determine that debug system tasks, such as $monitor and $strobe, are keeping track of the correct nets or registers, reset the simulation time to 0, and begin simulation again
The $reset system task tells a tool (for example a simulator) to return the processing of your design to its logical state at time 0. When a tool executes the $reset system task, it takes the following actions to stop the process (e.g., simulation):
• disables all concurrent activity, initiated in either initial and always procedural blocks in the source description or through interactive mode (disables, for example, all force and assign statements, the current $monitor system task, and any other active task)
• cancels all scheduled simulation events
After a simulation tool executes the $reset system task, the simulation is in the following state:
• The simulation time is 0.
• All registers and nets contain their initial values.
• The tool begins to execute the first procedural statements in all initial and always blocks.
Syntax:
$reset;
$reset(<stop_value>);
$reset(<stop_value>,<reset_value>);

$reset(<stop_value>,<reset_value>,<diagnostics_value>);

$restart
$save
$incsave
Three system tasks, $save, $restart, and $incsave, work in conjunction with one another to save the complete state of a tool into a permanent file such that the tool state can be reloaded at a later time and the tool can continue processing where it left off.
Syntax:
$save("<name_of_file>");
$restart("<name_of_file>");

$incsave("<incremental_filename>");

$scale
$scale(<hierarchical_name>);

The $scale function allows the user to take a time value from a module with one time unit to be used in a module with a different time unit. The time value is converted from the time unit of one module to the time unit of the module that invokes $scale.

$scope
$scope("<name>");

The $scope system task allows a particular level of hierarchy to be specified as the interactive scope for identifying objects. This task accepts a single parameter argument that must be the complete hierarchical name of a module, task, function, or named block. The initial setting of the interactive scope is the first top-level module.

$showscopes
$showscopes;$showscopes(n);

The $showscopes system task produces a complete list of modules, tasks, functions, and named blocks that are defined at the current scope level. An optional integer parameter can be given to $showscopes. A nonzero parameter causes all the modules, tasks, functions and named blocks in or below the current hierarchical scope to be listed. No parameter or a zero results in only objects at the current scope level to be listed.

$showvariables
$showvars
$showvars;$showvars(<list_of_variables>);
The $showvars system task produces status information for register and net variables, both scalar and vector. When invoked without parameters, $showvars displays the status of all variables in the current scope. When invoked with a <list_of_variables>, $showvars shows only the status of the specified variables. If the <list_of_variables> includes a bit-select or part-select of a register or net then the status information for all the bits of that register or net are displayed.

The system task $showvariables displays information similar to that of $showvars, but allows more control over the information displayed.

$stop
$stop;
$stop(n);
The $stop system task puts the tool (for example a simulator) into halt mode, issues an interactive command prompt, and passes control to the user. This task takes an optional expression parameter (0, 1, or 2) that determines what type of diagnostic message is printed. The amount of diagnostic messages output increases with the value of the optional parameter passed to $stop.

$timeformat
The $timeformat system task performs the following two functions:
1. It specifies how the %t format specification reports time information for the $write, $display, $strobe, $monitor, $fwrite, $fdisplay, $fstrobe, and $fmonitor system tasks.
2. It specifies the time unit for delays entered interactively.
Syntax:
$timeformat (<units_number>, <precision_number>, <suffix_string>, <minimum_field_width>);

NEXT

You may like to visit below pages -
Source - Verilog LRM 2005 Edition

Refreshing your brain with Verilog


Below are the link for a quick review of verilog language

http://www.tcnj.edu/~hernande/Eng312/TCNJ_Verilog(R)_V05.pdf

Click on main heading for detail information.

Lexical Element 

  • case sensitive 
  • keywords - lowercase
  • comments -  one line comments  start with " // " 
  • comments - more than one line -  start with "/*" and end with "*/"  
  • variable names have to start with an alphabetic character or underscore 
  • system task will start from "$" character 


  • Parameter
  • wire , wor, wand , tri0, tri1, supply0, supply1, trireg, tri, triand, trior  
  • reg
  • integer
  • time
  • real 
  • realtime
  • event
  • task
  • function
  • input , output, input 

  • `define
  • `ifdef , `else , `elsif , `endif
  • `include
  • `resetall
  • `timescale
  • `signed , `unsigned
  • `celldefine, `endcelldefine
  • `unconnected_drive pull0 | pull1
  • `nounconnected_drive 
  • `remove_netname , `noremove_netnames
  • `protect , `endprotect 

  • $display
  • $monitor
  • $strobe
  • $write
  • $fwrite
  • $fdisplay
  • $fmonitor
  • $time
  • $realtime
  • $finish
  • $showvars
  • $scale
  • $scope
  • $showscopes
  • $stop
  • $setup
  • $hold
  • $setuphold
  • $readmemb
  • $readmemh
  • $getpattern




and

always

assign

attribute

begin

buf

bufif0

bufif1
case
cmos
deassign
default
defparam
disable
else
endattribute
end
endcase
endfunction
endprimitive
endmodule
endtable
endtask
event
for
force
forever
fork
function
highz0
highz1
if
initial
inout
input
integer
join
large
medium
module
nand
negedge
nor
not
notif0
notif1
nmos
or
output
parameter
pmos
posedge
primitive
pulldown
pullup
pull0
pull1
rcmos
reg
release
repeat
rnmos
rpmos
rtran
rtranif0
rtranif1
scalared
small
specify
specparam
strong0
strong1
supply0
supply1
table
task
tran
tranif0
tranif1
time
tri
triand
trior
trireg
tri0
tri1
vectored
wait
wand
weak0
weak1
while
wire
wor









Source - http://www.verilog.org/verilog-ams/htmlpages/public-docs/lrm/2.3/VAMS-LRM-2-3.pdf




Parallel statement -    
fork ...... join

Conditional statement - 
if ..... else 
if .... else if .... else 
case 
casez
casex

Looping statement 
forever 
for ( ) 
repeat () 
while () 


Continuous Assignment  
wire abc = 5'd10 ;
assign abc = 5'd10 ; 
assign a = b ; 

Procedural Assignment 
initial 
always 
task
function

Blocking Assignment 
a = b ;
b = c ; 
c = a ; 

Non-Blocking Assignment 
a <= b ;
b <= c ;
c <= a ;
$finish 
$stop
$monitoron
$monitoroff
$dumpon
$dumpoff
$dumpfile
$dumplimit
$dumpflush
$dumpvars
$dumpall
$reset
$random
$realtobits
$bitstoreal 
$rtoi
$itor


$display 
$monitor 
$strobe 
$fdisply
$fmonitor
$fstrobe

$display(" Counting start - %AB " , count); 

AB = d  -> display in decimal
AB = h  -> display in hex 
AB = b  -> display in binary 
AB = o  -> display in octal
AB = c  -> display in  ACSII 
AB = v  -> display  net signal strength 
AB = s  -> display as string
AB = t  -> display in current time format 
AB = m  -> display hierarchical name 
AB = e  -> display real in scientific form
AB = f  -> display real in decimal form
AB = g  -> display real in shortest form

Waveform dump using $dump system task -
Syntax  -
$dumpfile(<filename>);
$dumpvars(<levels> <,<module|var>>* );
$dumpoff;
$dumpon;
$dumpall;
$dumplimit(<filesize>);
$dumpflush;
The $dumpfile system task specifies the name of the value change dump file.
The $dumpvars system task specifies the variables whose changing values a tool records in the value change dump file. The $dumpvars when invoked with no arguments dumps all variables in the design.
The $dumpoff system task stops a tool from recording value changes in the value change dump file.
The $dumpon system task allows a tool to resume recording value changes in the value change dump file.
The $dumpall system task creates a checkpoint that shows the current value of all variables being recorded in the value change dump file.
The $dumplimit system task sets the size of the value change dump file.
The $dumpflush system task empties the dump file buffer and ensures that all the data in that buffer is stored in the value change dump file.

initial begin
$dumpvar(<file>.wave);
$dumpvars();  // dump all
end

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