_TOP_MENU

Career Growth in VLSI Industry The Future of Semiconductor Semiconductor Companies
Count 0's n 1's SYNC n ASYNC FF Pattern Detection GREY TO BINARY CONV FIR FILTER PARITY CHECKER SQUARE ROOT ROUND ROBIN ALGO BINARY TO 7-SEGMENT 8-BIT ALU BINARY TO GREY CONV SYNCHRONOUS FIFO EDGE DETECTOR
Low Power Design Verification Low Power design Technique RTL for Low Power Design UPF for Low Power DesignLink 3 UPF Example Retention Cells UPF Link 3
Reset Recovery and Removal NAND Gate using Mux Async or Synchronous Reset for Asic XOR gate using NAND Error Correction n Detection AHB or AXI or AMBA 2 I2C or CAN Protocol MTBF Link 3 Link 2 Link 3 Link 2 Link 3
SDC File Samir Palnitkar Solution Timing Constraint Clock Gating Circuit Interview Question Target Library Vs Link Library Link 2
I2C IP UART IP SPI IP MicroWire IP Link 2 Link 2 Link 2
Quiz 1: Digital design Fundamentals Quiz2: Digital Design: CDC Link 1
VLSI Interview Q/A Interview Q/A on AXI Protocol Interview Q/A on Digital Design Interview Q/A General Topics Interview Q/A on PCIe Express Interview Q/A on Synthesis Interview Q/A on IC Fabrication Interview Q/A on Asynchronous FIFO
JOBs in VLSI JOB Portal Freshers Moving to Finland ? Sweden Salary for IT Professional Limited entry scope for Freshers 10 Things to remember
Donate us div>

Dec 28, 2016

Verilog Code for Round Robin Algorithm


Round Robin algorithm details :
Round Robin algorithm Verilog code :

What is Round Robin algorithm ?

Round-robin (RR) is one of the algorithms employed by process and network schedulers in computing.As the term is generally used, time slices (also known as time quanta) are assigned to each process in equal portions and in circular order, handling all processes without priority (also known as cyclic executive). Round-robin scheduling is simple, easy to implement, and starvation-free. Round-robin scheduling can also be applied to other scheduling problems, such as data packet scheduling in computer networks. It is an operating system concept.


Below is the diagram.




In the real situation, we can have a modified version of round robin.
Below feature can be include while designing a arbiter using round robin.
  1. If there are no requests,  which ever device/master send request, access will be given in next clock cycle.
  2. For some master, priority can be set. 
  3. Programmable delay to get the access if request is present. 

Below is the block diagram for round robin algorithm with 4 request and 4 grant.




Counter will be controlled by a state machine.




Verilog Code for Round Robin Algorithm : 

Below are the simulation results : 


In the same way, request/grant can be increased to n number.

Ref - https://en.wikipedia.org/wiki/Round-robin_scheduling

Posted by 5 comments:
Labels: ,
Subscribe to: Posts (Atom)