What is the difference between RTL design for ASIC and RTL design for FPGA?

 Everyone here already talked about the differences between FPGAs and ASICs.

Having designed both, I can tell you that design for ASICs can be quite different for FPGAs (and it could also be the same).

There is on major area of difference in coding and this has to do with clocks. FPGAs, due to their nature, run on a fairly slow clock (typically 50-100 MHz). ASICs can have clocks > 1 GHz. Because of this, RTL coding styles reflect these differences.

To meet performance requirements with ASICs, the internal buses in one's design can be much narrower than ones in an FPGA. When targeting FPGAs, you are forced to use very wide data buses.

Wth ASICs, you have complete flexibility in using dual-ported and two-ported SRAMs (and sometimes EDRAMs) which make designing FIFOs and larger internal caches easy and efficient. In FPGAs, your memory storage options are very limited. An FPGA may have a lot of onboard memory but it may be too far away from your logic or not organized in the most optimal way.

Furthermore, with ASICs, you have complete control on the kinds of I/O you support (if you need high-speed SerDes) or specialized I/O. With FPGAs, you are limited by whatever your FPGA vendor (I.e. Altera or Xilinx has built in).

If you are designing for both ASICs and FPGA, you may have to use a lot of 'ifdef statements to optimize your code for the two different targets. RTL written for FPGA will easily map to an ASIC technology but will be grossly inefficient. RTL written for an ASIC technology may not work at target speed in FPGAs and may need to be significantly re-written.

In terms of designing for low-power, in ASICs, in addition to clock gating, you can use separate voltage rails for parts of the ASIC or for memories vs core logic, to reduce leakage. With FPGAs, you have very limited control on power reduction.

One other major difference is that ASICs can accommodate analog components like A/D converters, D/A converters, multiple PLLs, analog filters, and power regulators. You would have to implement these externally when using an FPGA.