What are the opportunities in RTL coding in India and what basics should be possessed to settle in RTL coding?

 Good work in RTL is only opportunistic:

System integration is more about re-usability from existing projects, creating wrappers around IPs, directly integrating legacy IPs, etc.

IP development usually includes work on specific protocols - many categories of IPs have matured (like core processors, etc.) while others like high-speed serial interfaces always look for higher speeds and hence are in constant development.

Hot topics include work on:

high-speed serial peripheral interfaces like PCIE/ Ethernet/ USB, etc. - aim is to develop the next protocol version with higher bandwidth, lower latency and overall better performance

the industry shift towards Artificial Intelligence/ Machine Learning has spurred development of dedicated processors for AI/ML algorithms - since this field is in its nascent stage, there is huge scope for RTL development

open source focus towards processor development has re-kindled opportunities in RISC-V processor development - this is seen as a cheap alternative for ARM/x86 based processors - also in its nascent stage

Pre-requisites for RTL development:

Good understanding of digital VLSI logic design, processor design, etc.

combo and sequential logic: blocking vs non-blocking, flops vs gates

state machines - shift registers

adder, subtractor, multiply-and-accumulate, gray-codes

synchronous-fifo, asynchronous-fifo

clocking schemes, clock-domain-crossings

Good understanding of computer architecture

because writing RTL for 1-bit adder is no fun

how to divide logic into control-path and data-path

how many stages to use - higher the stages, higher the freq but more latency

command on Verilog

understanding the difference between synthesizable and non-synthesizable constructs

good RTL guy knows how many gates the logic will synthesize into - lesser the gates, the better the design in terms of area but should not impact performance

ability to write RTL by just seeing the timing diagram

reading RTL written by other people always helps - the more one reads, the more one knows

Good to know (if possible):

knowledge of std-cell library available

spending sometime in verification or emulation bring-up helps one understand the system-level perspective of how the RTL works

whereas spending time in implementation helps understand the physical limitations/ challenges faced