Physical Design - Answer1

 Expertise on any one P&R tools is must: It can be ICC or EDI or Talus or Atoptech or any other tool. It doesn't matter which tool you know, but you can never learn and appreciate P&R if you don't know the P&R tool.

1.Design Methodology and flow all the way from netlist to GDSII .

2. Synthesis: Good understanding of what happens in synthesis/DFT. Till couple of yrs ago, this was not required, but I think knowing it will give you the ability to do some incremental synthesis when required. Like impact of synthesis on routability aspects and what can be done etc. Sometimes pushing the synthesis little harder can have drastic impact (both positive and negative) in back end.

3. DFT: Knowing impacts of DFT and how it can effect timing closure , how different MBIST structures can create challenges for P&R engineers and how you can deal with it etc will help. Understand what happens in scan chain reordering, scan chain optimization etc and see where you can use it and under what context

4. Constraints Management : Most of the time backend engineers are given timing constraints to work with. But dont blindly use it. Have clear understanding of the various clock domain relationships, exceptions that are created like multi-cycle/false-path/max & min delay, IO constraints , clock latency and if any source latency is specified. Traditionally people over constrain their design quite a bit sometimes as high 25-35% . This might be overkill in P&R as tool might over buffer the design etc. Understanding the constraints will also give you a perspective on how the design is getting modeled as and so you can make appropriate decisions while doing floorplanning.

5. Understand the physical resources you have (meaning technology rules, whether its 9track or 12track, number of metal layers, which layers are thick etc) . Knowing whether you have more horizontal or vertical resources can also dictate your floorplan or at least you can make an attempt to create a floorplan that gives you more resources.

6. Data flow between various blocks/modules. You need to know which logic cluster talks to what and how intense is the traffic between 2 logic clusters.

7. Understanding memories , where splitting RAM's will help and knowing ahead how much to skew the clocks of the RAM

8. Understanding which pins are critical and where they should be placed in the context of top.

9. Very good understanding on the planned P&R tool. IMHO, you can claim to have a good understanding if you know the limitations of the tool, what optimization steps it does and where, where you can use those optimization tricks, how tool behaves when it has to make trade-off between timing vs congestion etc

10. Know TCL/Perl/Shell really well and I have seen folks using python as well, but since most EDA tools use TCL and work on Linux platforms, I would first concentrate on TCL/Shell programming and next Perl.

11. Know how to interpret timing reports accurately both P&R tool and Signoff tool

12. Know which timing violations to fix first among the following: transition, hold and setup.

13. How to implement the ECO (Both pre-mask and post-mask) and what kind of challenges they pose

14. Understand which optimizations might or can cause FV headaches.

15. Understand the TAP cells & cell spacing rule requirements

16. Understanding MVDD techniques and how it complicates things. Also, how to verify an multi-power domain design via UPF/CPF etc?

17. Timing Closure.

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