What is the best way to start learning to write synthesizable RTL Verilog code?

 Before moving on to the question directly let me first separate out the synthesizable and non-synthesizable construct in Verilog:-

Synthesizable:- module,endmodule,always block,parameter,task(without any delay),function,assign,if..else,while loop,for loop,case,casex,casez,ports like input,output,input,forever loop,begin,end,instantiation,disable block,wire,reg,localparam,static arrays,blocking and nonblocking assignments,all the operators of verilog,compiler directives.

Non-synthesizable:- force and release,wait statement,delay,event control statement,deassign,initial,fork and join,time,UDP.

Following are some of the points:-

Get a book on Verilog and start learning all the concepts related to it starting from the flow,data types,constructs,assignment,execution of the code,syntax and structure of the code. In short throughly understand Verilog first.

Next point is to understand the stratified event queue in Verilog and its execution semantics(you can refer LRM for that).From the event region you will understand the scheduling of the events.

The next step is to specifically use the synthesizable constructs of Verilog which I already mentioned above and avoid the use of non-synthesizable constructs.Clearly understood the difference between a behavioural model and synthesizable model.While writing the code, view it's structure in the form of hardware as the main point is to achieve concurrency unlike C which is sequential in nature.

The next step is to properly follow the coding guidelines of RTL like use of Nonblocking in sequential circuits and use of blocking in combinational circuits and mixing of these two should be avoided.Use of #0 assignment should also be avoided.

Proper use of compiler directive which helps in conditional compilation.

The next most important step is practice and writing more RTL codes.