4x1 multiplex demultiplex priority encoder decoder

🟩 1. 4x1 Multiplexer (MUX)

Function: Selects one input from 4 inputs and passes it to the output based on 2 selection lines.

Inputs:

• Data Inputs: I0, I1, I2, I3

• Select Lines: S0, S1

Output:

• Y

Truth Table:

S1	S0	Output Y
0	0	I0
0	1	I1
1	0	I2
1	1	I3

---

🟧 2. 1x4 Demultiplexer (DEMUX)

Function: Takes 1 input and routes it to one of 4 outputs, based on select lines.

Inputs:

• Data Input: D

• Select Lines: S0, S1

Outputs:

• Y0, Y1, Y2, Y3

Truth Table:

S1	S0	Y0	Y1	Y2	Y3
0	0	D	0	0	0
0	1	0	D	0	0
1	0	0	0	D	0
1	1	0	0	0	D

---

🟨 3. 4-to-2 Priority Encoder

Function: Encodes the highest-priority active input (from I3 to I0) into binary.

Inputs: I0, I1, I2, I3 (I3 has the highest priority)

Outputs: A1, A0 (Binary code of highest-priority input), V (Valid output)

Truth Table:

I3	I2	I1	I0	A1	A0	V
0	0	0	0	X	X	0
0	0	0	1	0	0	1
0	0	1	X	0	1	1
0	1	X	X	1	0	1
1	X	X	X	1	1	1

X = Don't care

---

🟦 4-to-16 Decoder (or 2-to-4 Decoder)

Function: Converts binary input into a single high output among many.

Let’s keep it to a 2-to-4 Decoder (to match the 2-bit output from the priority encoder or 4:1 MUX):

Inputs: A1, A0

Outputs: Y0, Y1, Y2, Y3

Truth Table:

A1	A0	Y0	Y1	Y2	Y3
0	0	1	0	0	0
0	1	0	1	0	0
1	0	0	0	1	0
1	1	0	0	0	1

---

🟩 1. 4x1 Multiplexer (MUX)

🔸 Logic Expression:

$$Y = (\overline{S1} \cdot \overline{S0} \cdot I0) + (\overline{S1} \cdot S0 \cdot I1) + (S1 \cdot \overline{S0} \cdot I2) + (S1 \cdot S0 \cdot I3)$$

🔸 Circuit Diagram (Conceptual):

     I0 ───┐
           │
     I1 ───┼──> Logic AND with select lines
           │
     I2 ───┼──> OR gate ──> Output Y
           │
     I3 ───┘
       ↑
     Select lines:
     S1 ──┐
          ├─> Control logic
     S0 ──┘

---

🟧 2. 1x4 Demultiplexer (DEMUX)

🔸 Logic Expressions:

• Y0 = D · $\overline{S1} \cdot \overline{S0}$

• Y1 = D · $\overline{S1} \cdot S0$

• Y2 = D · $S1 \cdot \overline{S0}$

• Y3 = D · $S1 \cdot S0$

🔸 Circuit Diagram (Conceptual):

            D
            │
        ┌───▼───┐
        │ ANDs  │
        └──┬─┬─┬┘
           │ │ │
          S0 S1 (Select lines)
           ↓ ↓
     Y0 <──┤ └──── S1=0, S0=0
     Y1 <──┤────── S1=0, S0=1
     Y2 <──┤────── S1=1, S0=0
     Y3 <───────── S1=1, S0=1

---

🟨 3. 4-to-2 Priority Encoder

🔸 Output Logic:

• V = I0 + I1 + I2 + I3

• A1 = I2 + I3

• A0 = (I1 · ¬I2 · ¬I3) + I3

🔸 Circuit Diagram:

Inputs: I3 (highest priority) ... I0
         ↓
     Priority logic
         ↓
      ┌──────┐
      │ ENCODER │
      └──────┘
       │   │
      A1  A0 (binary output)

---

🟦 4-to-1 Decoder (2-to-4 Decoder)

🔸 Logic Expressions:

• Y0 = $\overline{A1} \cdot \overline{A0}$

• Y1 = $\overline{A1} \cdot A0$

• Y2 = $A1 \cdot \overline{A0}$

• Y3 = $A1 \cdot A0$

🔸 Circuit Diagram:

     A1 ──┐
          │
     A0 ──┘
          ↓
      ┌──────┐
      │Decoder│
      └──────┘
   ↓   ↓   ↓   ↓
  Y0  Y1  Y2  Y3

---

VERILOG CODE : 

Perfect! Here's the Verilog code for each of the four components:

---

🟩 1. 4x1 Multiplexer (MUX)

module mux4x1 (
    input wire [3:0] I,       // Inputs I0 to I3
    input wire [1:0] S,       // Select lines S1, S0
    output wire Y             // Output
);
    assign Y = (S == 2'b00) ? I[0] :
               (S == 2'b01) ? I[1] :
               (S == 2'b10) ? I[2] :
                             I[3];
endmodule

---

🟧 2. 1x4 Demultiplexer (DEMUX)

module demux1x4 (
    input wire D,              // Single input
    input wire [1:0] S,        // Select lines S1, S0
    output wire [3:0] Y        // Outputs Y0 to Y3
);
    assign Y[0] = (S == 2'b00) ? D : 1'b0;
    assign Y[1] = (S == 2'b01) ? D : 1'b0;
    assign Y[2] = (S == 2'b10) ? D : 1'b0;
    assign Y[3] = (S == 2'b11) ? D : 1'b0;
endmodule

---

🟨 3. 4-to-2 Priority Encoder

module priority_encoder_4to2 (
    input wire [3:0] I,       // I3 (highest) to I0
    output reg [1:0] Y,       // Encoded output
    output reg V              // Valid output
);
    always @(*) begin
        V = 1'b1;
        casez (I)
            4'b1???: Y = 2'b11; // I3
            4'b01??: Y = 2'b10; // I2
            4'b001?: Y = 2'b01; // I1
            4'b0001: Y = 2'b00; // I0
            default: begin
                Y = 2'b00;
                V = 1'b0;       // No input is high
            end
        endcase
    end
endmodule

---

🟦 4-to-1 Decoder (2-to-4 Decoder)

module decoder2to4 (
    input wire [1:0] A,      // Inputs A1, A0
    output wire [3:0] Y      // Outputs Y0 to Y3
);
    assign Y[0] = (~A[1]) & (~A[0]);
    assign Y[1] = (~A[1]) &  A[0];
    assign Y[2] =  A[1]  & (~A[0]);
    assign Y[3] =  A[1]  &  A[0];
endmodule

---