Q. How to dump waveform using command line option in VCS ?
initial begin
$vcspluson();
end
If you are trying to dump VCD format, it is very obvious that this file occupies more space because it contains ASCII format (readable).
If you are trying to dump as VCS's own format called VPD, then you have the following control over that.
$vcdplusfile("my_dump.vpd");
$vcdpluson(<level>, <scope>);
ex: $vcdpluson(0, top.dut.sub);
<level> - default is 0. Dumps all the levels.
$vcdplusoff(<level>, <scope>);
ex: $vcdplusoff(2, top.dut.sub.sub_2);
<level> - default is 0. Switch offs the dump upto the specified
levels.
Q. How to dump waveform in VHDL ?
A. I am searching , if you know please put that in comments.
initial begin
$vcdpluson(0,tb);
$fsdbDumpvars;
$dumpfile("file.vcd");
$dumpvars();
end
Dumping of signal value changes in VCD format can be enabled in verilog by including the $dumpvars system task.
In addition to this method, VCS provides a way to enable VCD dumping at compile time.
This can be achieved by including the following switch at compile time: "+vcs+dumpvars[+filename]"
For example, consider the following case:
cat test.v
module test;
reg clk;
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
#100 $finish;
end
endmodule
vcs test.v -V -l logfile -R +vcs+dumpvars+test.vcd
The $dumpvars system task is not specified in the verilog code above. Instead, VCD dumping is enabled with the addition of the compile time switch "+vcs+dumpvars+test.vpd".
The result is equivalent to calling the following system tasks:
$dumpvars;
$dumpfile("test.vpd");
If the filename is not specified (ie. only +vcs+dumpvars is used), then the filename defaults to "verilog.dump".
If both the system task ($dumpvars) and the compile-time switch (+vcs+dumpvars) are specified, then the compile-time switch takes precedence.
No additional verilog code is needed when enabling VCD dumping using the compile time switch.
Put your comments ... if you like it.
Thanks
