Physical Aware Synthesis

Physical aware synthesis is a design methodology in electronic design automation (EDA) that takes into account the physical characteristics of the integrated circuit (IC) during the synthesis process.

In traditional synthesis flows, the design is first synthesized into a netlist, and then the physical implementation details are considered during the placement and routing stages. However, this approach can lead to suboptimal results, as the synthesis stage does not consider the physical constraints of the IC, such as area, power, and timing.

Physical aware synthesis, on the other hand, integrates the physical implementation details into the synthesis stage. This allows the synthesis tool to make more informed decisions about the design, taking into account the physical characteristics of the IC, such as the available area, power consumption, and timing constraints.

The benefits of physical aware synthesis include:

Improved design quality:

By considering the physical implementation details during synthesis, the design is more likely to meet the required specifications and constraints.

Reduced design iterations:

Physical aware synthesis can reduce the number of design iterations required to achieve a working design, as the synthesis tool can make more informed decisions about the design.

Faster design closure: 

Physical aware synthesis can help to accelerate the design closure process, as the synthesis tool can quickly identify and resolve potential issues.

Some of the key techniques used in physical aware synthesis include:

Physical-aware modeling:

This involves creating models of the physical implementation details, such as area, power, and timing, and using these models to guide the synthesis process.

Placement-aware synthesis:

This involves considering the placement of the design components during the synthesis stage, to ensure that the design can be efficiently placed on the IC.

Routing-aware synthesis:

This involves considering the routing of the design components during the synthesis stage, to ensure that the design can be efficiently routed on the IC.

Some of the tools that support physical aware synthesis include:

Synopsys Design Compiler

Cadence Genus Synthesis Solution

Mentor Graphics Catapult


Inputs
Physical aware synthesis requires a floorplan DEF as input, which contains information such as IO port placements, blockages, and die area. It also uses an RC co-efficient file to calculate wire delay values.


different companies followed different flows and tools but basic fundamentals are the same. 

you need below info to start the physical aware synthesis. 

Die boundary 

block abstract if any 

memory size , they are usually having def or lef 

def/lef for hard macros 

once you have those inputs , you start creating floorplan and place those macros at appropriate places , tools also support auto_placement which can be useful to start the floorplan. 

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