4-bit DMUX verilog code

 Here's a Verilog code for a 4-bit Demultiplexer (Demux). In a 4-bit Demux, a 4-bit input is routed to one of four outputs based on the selection input.

4-bit Demux Logic

A Demux takes a single 4-bit input and routes it to one of four 4-bit outputs depending on the select signal. The sel input will decide which of the four outputs will receive the input data. Here is the Verilog code for this functionality:

Verilog Code for 4-bit Demux:

module demux4to4 (
    input [3:0] data_in,   // 4-bit input data
    input [1:0] sel,       // 2-bit select signal
    output reg [3:0] out0, // Output 0
    output reg [3:0] out1, // Output 1
    output reg [3:0] out2, // Output 2
    output reg [3:0] out3  // Output 3
);

    always @ (data_in or sel) begin
        // Default all outputs to 0
        out0 = 4'b0000;
        out1 = 4'b0000;
        out2 = 4'b0000;
        out3 = 4'b0000;

        // Select output based on the sel input
        case (sel)
            2'b00: out0 = data_in; // If sel = 00, route data_in to out0
            2'b01: out1 = data_in; // If sel = 01, route data_in to out1
            2'b10: out2 = data_in; // If sel = 10, route data_in to out2
            2'b11: out3 = data_in; // If sel = 11, route data_in to out3
            default: begin
                out0 = 4'b0000;
                out1 = 4'b0000;
                out2 = 4'b0000;
                out3 = 4'b0000;
            end
        endcase
    end

endmodule

Explanation of the Code:

1. Inputs:

   • data_in: A 4-bit input signal that will be routed to one of the 4 outputs.
   • sel: A 2-bit selection signal that determines which output will receive the data_in.

2. Outputs:

   • out0, out1, out2, out3: The 4-bit output signals. Only one of these will carry the data_in value based on the sel value.

3. Behavior:

   • In the always block, the output signals are set to 4'b0000 by default.
   • A case statement is used to check the value of sel and route data_in to the corresponding output (out0, out1, out2, or out3).

4. Case Breakdown:

   • If sel = 00, data_in is routed to out0.
   • If sel = 01, data_in is routed to out1.
   • If sel = 10, data_in is routed to out2.
   • If sel = 11, data_in is routed to out3.

Example Usage:

• For data_in = 4'b1010 and sel = 2'b01, out1 will be assigned 4'b1010, and all other outputs will be 4'b0000.