RTL DIGITAL DESIGN : January 2026

Jan 7, 2026

UPF : Power Switch

UPF: Power Switch Details

What is a Power Switch?
A power switch represents a set of header (PMOS) or footer (NMOS) transistors that connect/disconnect a power domain using enable/control signals—allowing blocks to be shut down during idle mode.

Why a Power Switch is needed

Reduce leakage power
Enable power-gated domains (power islands)
Essential for mobile / low-power SoC designs

Where it is used

VDD → Power-gated domain (header switch)
Power-gated domain → VSS (footer switch)

Key UPF elements involved

create_power_domain
create_supply_port
create_supply_net
create_power_switch
set_domain_supply_net

Simple UPF Power Switch example

create_power_domain PD_CORE
create_supply_port VDD
create_supply_port VSS
create_supply_net VDD
create_supply_net VSS
connect_supply_net VDD -ports VDD
connect_supply_net VSS -ports VSS

create_power_switch PSW_CORE \
  -domain PD_CORE \
  -input_supply_port  {VDD VDD} \
  -output_supply_port {VDD_SW VDD} \
  -control_port {PS_EN} \
  -on_state {ON PS_EN}

Meaning

PSW_CORE → Power switch name
VDD → VDD_SW → Switched power
PS_EN → Enable signal
When PS_EN = 1 → Power ON
When PS_EN = 0 → Power OFF

Header vs Footer switch

Type	Transistor	Position	Common use
Header	PMOS	Between VDD & block	Low noise
Footer	NMOS	Between block & GND	Area efficient

Power switch with isolation & retention (typical flow)

Power switch OFF
Isolation enabled
State retained (if needed)
Power switch ON
De-isolation

Real-world SoC usage

CPU core sleep mode
GPU power islands
Peripheral shutdown blocks

Timing-safe power-up sequence (UPF)

This sequence avoids X-propagation, crowbar current, and timing violations during wake-up.

Power-Up Order (Recommended)

Keep Isolation ON (clamp outputs to a known value)
Enable Power Switch (ramp-up)
Wait for Power Good (PG)
Restore Retention Registers
Release Reset
Enable Clock
Disable Isolation

set_isolation ISO_CORE -domain PD_CORE -clamp_value 0
# Enable power switch
# PS_EN = 1

wait (PWR_GOOD == 1);

set_retention_control RET_CORE -restore_signal RET_RESTORE
# Release reset
# RESET_N = 1
# Enable clock
# CLK_EN = 1

set_isolation_control ISO_CORE -isolation_signal ISO_EN -deassert

Golden Rule (Interview Favorite):
Isolation ON → Power ON → Power Good → Retention Restore → Reset Release → Clock ON → Isolation OFF

What happens if sequence is wrong?

Mistake	Result
Isolation OFF before power	X-propagation
Clock ON before power	Short-circuit current
Reset before power good	Unknown state
No PG wait	Timing failures

UPF Interview Questions & Answers

Q1. What is a power switch in UPF?

Ans: A power switch models header/footer transistors used to connect or disconnect power to a domain for leakage reduction.

Q2. Why is isolation required during power-up?

Ans: To prevent unknown (X) values from propagating from powered-off domains into active logic.

Q3. What is Power-Good (PG) signal?

Ans: A signal indicating that the supply voltage has reached a stable, safe operating level.

Q4. Difference between isolation and retention?

Isolation	Retention
Protects outputs	Preserves internal state
Mandatory	Optional
Active when power OFF	Active before power OFF

Q5. Why clocks are enabled last?

Ans: To prevent spurious switching and timing violations during unstable power.

Q6. What is inrush current and how do you avoid it?

Ans: Sudden current surge during power-up; avoided using staggered power switches or ramp-controlled enable.

Q7. Header vs Footer power switch?

Header	Footer
PMOS	NMOS
Low noise	Area efficient
Near VDD	Near GND

Q8. What happens if isolation is forgotten in UPF?

Ans: Functional simulation may pass, but gate-level simulation shows X-propagation and silicon failure.

Q9. Can a power-gated domain be clocked?

Ans: No. Clock must be gated OFF before power OFF and enabled only after power-up stabilization.

Q10. What checks ensure timing-safe power-up?

Ans:

Power-aware STA
UPF consistency checks
PG signal timing validation
Isolation/retention sequencing verification

“A timing-safe power-up ensures isolation first, stable power next, state restore, then clocks—never the other way around.”

UPF: Details on Level Shifter UPF Quiz: Power Switch UPF Quiz: Level Shifter

UPF Quiz : On Power Switch

UPF • Power-Up Sequence

UPF Power-Up & Power Switch Quiz

Comment if you got 15/15

Jan 5, 2026

QUIZ - On UPF - 5 (level Shifter)

⚡ Level Shifter Quiz

Time Left: 300 sec

Jan 2, 2026

Low Power Design : Level Shifter

Low-Power Design: Level Shifters

A level shifter is a circuit used in low-power digital design to safely transfer signals between blocks operating at different voltage levels (VDDs). They are critical in multi-voltage (multi-VDD) and power-gated SoC designs.

Key idea: Whenever a signal crosses from one voltage domain to another, it must be protected to avoid reliability issues, incorrect logic levels, leakage, and back-powering.

Why level shifters are needed

Prevents over-voltage stress that can damage transistors
Ensures logic '1' is recognized correctly at the receiving voltage
Reduces leakage current from high-VDD to low-VDD domains
Prevents back-powering when one domain is power-gated OFF

Typical low-power SoC scenario

Block	Supply
Always-ON (AON)	1.0 V
Logic core	0.8 V
High-performance	1.2 V

Signals crossing these domains must use level shifters.

Types of level shifters

1) Low-to-High (Up-shifter)

Converts lower voltage logic to higher voltage
Most common type
Often uses cross-coupled PMOS structure

Example: 0.8 V -> 1.2 V

2) High-to-Low (Down-shifter)

Converts higher voltage logic to lower voltage
Often simpler (sometimes a buffer is enough, but leakage must be checked)

Example: 1.2 V -> 0.8 V

3) Bidirectional level shifter

Used in buses (I2C, GPIO, open-drain style interfaces)
Direction can change dynamically

Where level shifters are placed

Situation	Typical placement
Signal enters higher-VDD domain	At receiver side (destination)
Signal enters lower-VDD domain	Often at sender side (source) to avoid over-voltage at destination
Power-gated block crossings	Depends on UPF policy + isolation strategy

Low-power design considerations

1) Leakage power

Level shifters can leak if always powered
Use high-Vt cells, power-gated LS (when allowed), or retention-aware solutions

2) Dynamic power

Dynamic power is proportional to C x V^2 x f. Up-shifters increase switching energy because they drive at higher VDD and add capacitance.

Tip: minimize number of crossings.

3) Interaction with power gating

If signals come from an OFF domain, they can float or become X. Usually you need isolation before level shifting:
OFF domain -> Isolation -> Level Shifter -> ON domain

If signals go into an OFF domain, the level shifter must remain powered (typically in AON) or the output may collapse.

4) Always-ON requirement

Wake-up, reset, and handshake signals often require LS placed in the AON domain.

Level shifters vs isolation cells

Feature	Level Shifter	Isolation Cell
Voltage conversion	Yes	No
Blocks leakage/back-powering	Not guaranteed	Yes
Prevents X propagation from OFF domain	No	Yes
Used across power domains	Yes	Yes

Important: In real low-power SoCs, both isolation and level shifting are often required together.

UPF example (intent)

create_power_domain PD_LOW

create_power_domain PD_HIGH

set_level_shifter LS_L2H \

  -from PD_LOW \

  -to PD_HIGH \

  -location to

With UPF, EDA tools can automatically insert the correct level shifter type and handle placement/connectivity based on your rules.

Common interview questions on level shifters

Q: Why are level shifters power-hungry?
A: They drive signals at higher VDD and add extra capacitance (higher switching energy).

Q: Can isolation replace level shifters?
A: No. Isolation does not change voltage levels; it clamps values when a domain is OFF.

Q: What happens if a level shifter is placed in a switched-off domain?
A: Output collapses or becomes invalid, causing functional failures.

More interview + concept-checking questions (Basic to Advanced)

Below are additional questions grouped by topic for interview preparation.

Basic concepts

What is a level shifter and why is it required in low-power design?
Can a buffer replace a level shifter? When and why?
What happens if a low-VDD output directly drives a high-VDD input?
Difference between L2H and H2L level shifters?
Are level shifters combinational or sequential?
Can level shifters introduce delay? Why?

Placement and power domains

Where to place a level shifter: source or destination domain? Why?
Why are some level shifters placed in Always-ON (AON) domain?
Can level shifters be power-gated?
What is back-powering, and how do you prevent it?
Do all signals crossing domains need level shifters?

Level shifter vs isolation

Difference between level shifter and isolation cell?
Why is isolation often needed along with level shifters?
For OFF -> ON crossings: Isolation then Level Shifter or Level Shifter then Isolation? Explain.

Timing, STA, and UPF

How are level shifters treated in STA?
Can level shifters cause hold violations? Why?
Do designers instantiate level shifters in RTL, or are they inserted by tools?
Explain UPF command: set_level_shifter -from PD1 -to PD2 -location to

Debug scenarios

Chip works at typical corner but fails at low voltage - what level shifter issues could cause this?
Simulation clean but silicon fails - what LS problems to suspect?
X-propagation seen after power-up - LS or isolation issue?

Quiz on UPF - MCQ

Glitch Free clock gating cells in digital design

This is one of the basic question asked in digital design interviews. Glitch on clock is very dangerous .

Glitch-Free Clock Gating Cells in Digital Design

Clock gating is used to reduce dynamic power by stopping the clock to parts of a circuit when they are not active. A glitch-free clock gating cell (CGC) ensures that the gated clock does not produce spurious pulses (glitches) that could cause incorrect behavior in sequential logic.

⸻

Why glitches happen in naive clock gating

If you simply gate a clock using an AND/OR gate:

gated_clk = clk & enable

Problems:

• enable may change while clk is HIGH

• This can create short pulses or missing edges

• Flip-flops may capture incorrect data or go metastable

⸻

Key idea of glitch-free clock gating

👉 Latch the enable signal only when the clock is in its inactive phase

Then use the latched enable to gate the clock.

⸻

Standard glitch-free clock gating structure

For positive-edge triggered flip-flops

Components:

1. Level-sensitive latch (transparent when clk = 0)

2. AND gate

enable

+-----------+

| LATCH | (transparent when clk = 0)

+-----------+

clk -----> AND ----------------> gated_clk

Operation:

• When clk = 0:

enable can safely change → latch updates

• When clk = 1:

latch holds its value → no glitch

• AND gate ensures clock passes only when latched enable = 1

⸻

RTL example (synthesizable, CGC-friendly)

module clock_gating (

input wire clk,

input wire enable,

output wire gated_clk

);

reg enable_latched;

always @(clk or enable) begin

if (!clk)

enable_latched <= enable;

end

assign gated_clk = clk & enable_latched;

endmodule

⚠️ Note:

This style is recognized by synthesis tools and mapped to a standard clock gating cell from the library.

⸻

Integrated Clock Gating (ICG) Cells

In real ASIC flows, designers do not code gates manually.

Libraries provide ICG cells with:

• Built-in latch

• AND/OR logic

• Test enable (scan_enable)

• Low skew and low insertion delay

Typical ICG ports:

• CLK – input clock

• EN – functional enable

• SE – scan enable (forces clock ON during test)

• GCLK – gated clock output

⸻

With scan/test support

effective_enable = EN | SE

This ensures clocks are not blocked during:

• Scan shift

• ATPG

• DFT testing

⸻

Best practices

✅ Use library-provided ICG cells

✅ Place CGCs close to clock source

✅ Avoid gating clocks with combinational logic

✅ Ensure enable is synchronous to clock domain

✅ Use clock gating checks in STA tools

❌ Never gate clocks manually with AND/OR gates in final RTL

⸻

FPGA vs ASIC note

• ASIC: Clock gating is common and recommended

• FPGA: Avoid clock gating; use clock enable (CE) instead

⸻

Summary

Aspect Glitch-Free Clock Gating

Glitch risk Eliminated

Power saving High

Uses latch Yes

ASIC friendly Yes

DFT support Yes

Jan 1, 2026

class 8 CBSE science revision test paper free download A4

Here is the link to download the class 8 science CBSE pattern revision test paper.

Class 8 CBSE Science Revision test paper Set A

Jan 19, 2026

C / C++ Interview MCQ Test

Decoder: Huffman Coding 📟

Jan 7, 2026

Why a Power Switch is needed

Where it is used

Key UPF elements involved

Simple UPF Power Switch example

Meaning

Header vs Footer switch

Power switch with isolation & retention (typical flow)

Real-world SoC usage

Timing-safe power-up sequence (UPF)

What happens if sequence is wrong?

UPF Interview Questions & Answers

UPF Power-Up & Power Switch Quiz

Jan 5, 2026

⚡ Level Shifter Quiz

Jan 2, 2026

Low-Power Design: Level Shifters

Why level shifters are needed

Typical low-power SoC scenario

Types of level shifters

Where level shifters are placed

Low-power design considerations

Level shifters vs isolation cells

UPF example (intent)

Common interview questions on level shifters

More interview + concept-checking questions (Basic to Advanced)

Jan 1, 2026

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