Low Power Design : Level Shifter

Low-Power Design: Level Shifters

A level shifter is a circuit used in low-power digital design to safely transfer signals between blocks operating at different voltage levels (VDDs). They are critical in multi-voltage (multi-VDD) and power-gated SoC designs.

Key idea: Whenever a signal crosses from one voltage domain to another, it must be protected to avoid reliability issues, incorrect logic levels, leakage, and back-powering.

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Why level shifters are needed

• Prevents over-voltage stress that can damage transistors
• Ensures logic '1' is recognized correctly at the receiving voltage
• Reduces leakage current from high-VDD to low-VDD domains
• Prevents back-powering when one domain is power-gated OFF

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Typical low-power SoC scenario

Block	Supply
Always-ON (AON)	1.0 V
Logic core	0.8 V
High-performance	1.2 V

Signals crossing these domains must use level shifters.

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Types of level shifters

1) Low-to-High (Up-shifter)

• Converts lower voltage logic to higher voltage
• Most common type
• Often uses cross-coupled PMOS structure

Example: 0.8 V -> 1.2 V

2) High-to-Low (Down-shifter)

• Converts higher voltage logic to lower voltage
• Often simpler (sometimes a buffer is enough, but leakage must be checked)

Example: 1.2 V -> 0.8 V

3) Bidirectional level shifter

• Used in buses (I2C, GPIO, open-drain style interfaces)
• Direction can change dynamically

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Where level shifters are placed

Situation	Typical placement
Signal enters higher-VDD domain	At receiver side (destination)
Signal enters lower-VDD domain	Often at sender side (source) to avoid over-voltage at destination
Power-gated block crossings	Depends on UPF policy + isolation strategy

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Low-power design considerations

1) Leakage power

• Level shifters can leak if always powered
• Use high-Vt cells, power-gated LS (when allowed), or retention-aware solutions

2) Dynamic power

Dynamic power is proportional to C x V^2 x f. Up-shifters increase switching energy because they drive at higher VDD and add capacitance.

Tip: minimize number of crossings.

3) Interaction with power gating

If signals come from an OFF domain, they can float or become X. Usually you need isolation before level shifting:
OFF domain -> Isolation -> Level Shifter -> ON domain

If signals go into an OFF domain, the level shifter must remain powered (typically in AON) or the output may collapse.

4) Always-ON requirement

Wake-up, reset, and handshake signals often require LS placed in the AON domain.

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Level shifters vs isolation cells

Feature	Level Shifter	Isolation Cell
Voltage conversion	Yes	No
Blocks leakage/back-powering	Not guaranteed	Yes
Prevents X propagation from OFF domain	No	Yes
Used across power domains	Yes	Yes

Important: In real low-power SoCs, both isolation and level shifting are often required together.

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UPF example (intent)

create_power_domain PD_LOW
create_power_domain PD_HIGH

set_level_shifter LS_L2H \
-from PD_LOW \
-to PD_HIGH \
-location to

With UPF, EDA tools can automatically insert the correct level shifter type and handle placement/connectivity based on your rules.

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Common interview questions on level shifters

Q: Why are level shifters power-hungry?
A: They drive signals at higher VDD and add extra capacitance (higher switching energy).

Q: Can isolation replace level shifters?
A: No. Isolation does not change voltage levels; it clamps values when a domain is OFF.

Q: What happens if a level shifter is placed in a switched-off domain?
A: Output collapses or becomes invalid, causing functional failures.

More interview + concept-checking questions (Basic to Advanced)

Below are additional questions grouped by topic for interview preparation.

Basic concepts

1. What is a level shifter and why is it required in low-power design?
2. Can a buffer replace a level shifter? When and why?
3. What happens if a low-VDD output directly drives a high-VDD input?
4. Difference between L2H and H2L level shifters?
5. Are level shifters combinational or sequential?
6. Can level shifters introduce delay? Why?

Placement and power domains

7. Where to place a level shifter: source or destination domain? Why?
8. Why are some level shifters placed in Always-ON (AON) domain?
9. Can level shifters be power-gated?
10. What is back-powering, and how do you prevent it?
11. Do all signals crossing domains need level shifters?

Level shifter vs isolation

12. Difference between level shifter and isolation cell?
13. Why is isolation often needed along with level shifters?
14. For OFF -> ON crossings: Isolation then Level Shifter or Level Shifter then Isolation? Explain.

Timing, STA, and UPF

15. How are level shifters treated in STA?
16. Can level shifters cause hold violations? Why?
17. Do designers instantiate level shifters in RTL, or are they inserted by tools?
18. Explain UPF command: set_level_shifter -from PD1 -to PD2 -location to

Debug scenarios

19. Chip works at typical corner but fails at low voltage - what level shifter issues could cause this?
20. Simulation clean but silicon fails - what LS problems to suspect?
21. X-propagation seen after power-up - LS or isolation issue?

Quiz on UPF - MCQ