Low Power Design : Level Shifter

 
Level Shifter for Low Power Design. : 
Low Power Design Level Shifter : 

Low-Power Design: Level Shifters

A level shifter is a circuit used in low-power digital design to safely transfer signals between blocks operating at different voltage levels (VDDs). They are critical in multi-voltage (multi-VDD) / power-gated designs.

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Why level shifters are needed

Without level shifters:

• Over-voltage stress can damage transistors

• Logic ‘1’ may not be recognized correctly

• Leakage current can flow from high-VDD to low-VDD domains

• Power-gated blocks can back-power other domains

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Typical low-power SoC scenario

Block Supply

Always-ON (AON) 1.0 V

Logic core 0.8 V

High-performance 1.2 V

Signals crossing these domains must use level shifters.

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Types of level shifters

1️⃣ Low-to-High (Up-Shifter)

• Converts lower voltage logic to higher voltage

• Most common

• Usually cross-coupled PMOS structure

Example:

0.8 V → 1.2 V

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2️⃣ High-to-Low (Down-Shifter)

• Converts higher voltage logic to lower voltage

• Often simpler

• Sometimes just a buffer (but leakage must be controlled)

Example:

1.2 V → 0.8 V

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3️⃣ Bidirectional Level Shifter

• Used in buses (I²C, GPIO)

• Direction controlled dynamically

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Where level shifters are placed

Situation Placement

Signal enters higher-VDD domain At receiver side

Signal enters lower-VDD domain At sender side

Power-gated block Before isolation or after isolation (depends on policy)

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Low-Power Design Considerations

🔋 1. Leakage Power

• Level shifters can leak if always powered

• Use:

• High-Vt devices

• Power-gated level shifters

• Retention-aware designs

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⚡ 2. Dynamic Power

Dynamic power ∝ C × V² × f

Up-shifters increase:

• Load capacitance

• Switching energy (higher VDD)

➡️ Minimize number of crossings

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🛑 3. Interaction with Power Gating

Case: Signal from OFF domain → ON domain

Problem:

• Floating / X values

Solution:

• Isolation cells before level shifters

OFF domain → Isolation → Level Shifter → ON domain

Case: Signal from ON domain → OFF domain

• Level shifter must be in always-on domain

• Otherwise output may collapse

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🧱 4. Always-ON Requirement

Some level shifters must remain powered:

• Reset

• Wake-up signals

• Handshake signals

These are placed in AON power domain.

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Level Shifters vs Isolation Cells

Feature Level Shifter Isolation Cell

Voltage conversion ✅ Yes ❌ No

Blocks leakage ❌ No ✅ Yes

Prevents X-propagation ❌ ✅

Used across power domains ✅ ✅

👉 Often both are required.

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Example (conceptual RTL – tool inserts cells)

// Designer intent (no explicit level shifter)

assign data_to_high = data_from_low;

Actual implementation (by synthesis + UPF)

LOW_VDD → Level Shifter → HIGH_VDD

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UPF (Unified Power Format) intent example

create_power_domain PD_LOW

create_power_domain PD_HIGH

set_level_shifter LS_L2H \

   -from PD_LOW \

   -to PD_HIGH \

   -location to

EDA tools automatically:

• Insert correct LS cells

• Choose L2H or H2L

• Handle placement & connectivity

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Common interview questions

Q: Why are level shifters power-hungry?

➡️ Because they drive signals at higher VDD and add extra capacitance.

Q: Can isolation replace level shifters?

➡️ No. Isolation does not change voltage levels.

Q: What happens if level shifter is placed in switched-off domain?

➡️ Output collapses → functional failure.

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Best Practices

✅ Minimize voltage crossings

✅ Place LS near destination domain

✅ Keep LS in always-on domain if needed

✅ Combine with isolation properly

✅ Use library-qualified LS cells only

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Summary

• Level shifters are mandatory in multi-VDD low-power designs

• Critical for signal integrity, leakage control, and reliability

• Correct placement & power intent (UPF) is essential

Interview questions on level shifter : 

Here are more interview + concept-checking questions on Level Shifters, moving from basic → advanced → real-silicon / debug level, focused on low-power VLSI / SoC design.

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🔹 Basic Concept Questions

1. What is a level shifter and why is it required in low-power design?

2. Can a buffer replace a level shifter? When and why?

3. What happens if a signal from a low-VDD domain directly drives a high-VDD flop?

4. Why are level shifters not required within a single voltage domain?

5. Difference between L2H and H2L level shifters?

6. Why do up-shifters consume more power than down-shifters?

7. Are level shifters combinational or sequential?

8. Can level shifters introduce delay? Why?

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🔹 Placement & Power Domain Questions

9. Where should a level shifter be placed: source domain or destination domain? Why?

10. What happens if a level shifter is placed in a power-gated (switched-off) domain?

11. Why are some level shifters placed in the Always-ON (AON) domain?

12. Can level shifters be power-gated?

13. What is back-powering, and how do level shifters prevent it?

14. Do all signals crossing power domains need level shifters?

15. What happens if voltage difference between domains is very small?

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🔹 Level Shifter vs Isolation

16. Difference between level shifter and isolation cell?

17. Why is isolation often needed along with level shifters?

18. Order question:

Isolation → Level Shifter OR Level Shifter → Isolation?

Explain with OFF → ON case.

19. Can an isolation cell do voltage conversion?

20. What kind of bugs occur if isolation is missing but level shifter is present?

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🔹 Timing & STA Questions

21. How are level shifters treated in STA?

22. Do level shifters affect setup and hold timing?

23. Can level shifters cause hold violations? Why?

24. Are level shifters considered part of clock path or data path?

25. How does voltage scaling impact level shifter delay?

26. Why do level shifters need special timing libraries?

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🔹 UPF / CPF / Tool Flow Questions

27. Do designers instantiate level shifters in RTL?

28. How does UPF help in level shifter insertion?

29. Explain this UPF command:

set_level_shifter -from PD1 -to PD2 -location to

30. What does -location to mean?

31. What happens if level shifter rules are missing in UPF?

32. Can tools insert wrong type of level shifter? When?

33. How do tools decide between L2H and H2L?

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🔹 Clock & Reset Related Questions

34. Can clocks pass through level shifters?

35. Why is clock level shifting risky?

36. How are gated clocks handled across voltage domains?

37. Should reset signals use level shifters?

38. What happens if async reset comes from a higher-VDD domain?

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🔹 Advanced / Silicon-Level Questions

39. What is contention current in level shifters?

40. Why cross-coupled PMOS are used in up-shifters?

41. What causes metastability in level shifters?

42. How does temperature affect level shifter behavior?

43. Why are level shifters hotspots for IR drop?

44. What is crowbar current in level shifters?

45. How do you reduce leakage in always-on level shifters?

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🔹 Debug & Failure Scenarios (Very Important)

46. Chip works at typical corner but fails at low voltage – role of level shifters?

47. Simulation is clean but silicon fails – what LS issues to suspect?

48. X-propagation seen after power-up – LS or isolation issue?

49. Scan chain broken – could level shifter be the reason?

50. Why do wake-up signals fail if LS is wrongly powered?

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🔹 Short Answer (Rapid-Fire)

51. Can level shifters latch data?

52. Do level shifters support bidirectional signals?

53. Are level shifters technology dependent?

54. Do they exist in standard cell libraries?

55. Can level shifters be shared across multiple signals?

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🔹 One-Line Concept Checks (Interview Gold)

56. “Isolation blocks values; level shifter changes voltage” – explain.

57. Why LS must be powered even when logic is OFF?

58. Why LS insertion increases congestion?

59. Why multi-bit LS cells are preferred?

60. Why LS are avoided on high-frequency paths?

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🔹 Case-Study Question

61.

A signal goes from 0.7 V domain (power-gated) to 1.0 V always-on domain.

• What cells are needed?

• Where should they be placed?

• What happens during OFF state?

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