Glitch Free clock gating cells in digital design

 

This is one of the basic question asked in digital design interviews. Glitch on clock is very dangerous . 

Glitch-Free Clock Gating Cells in Digital Design

Clock gating is used to reduce dynamic power by stopping the clock to parts of a circuit when they are not active. A glitch-free clock gating cell (CGC) ensures that the gated clock does not produce spurious pulses (glitches) that could cause incorrect behavior in sequential logic.

⸻

Why glitches happen in naive clock gating

If you simply gate a clock using an AND/OR gate:

gated_clk = clk & enable

Problems:

• enable may change while clk is HIGH

• This can create short pulses or missing edges

• Flip-flops may capture incorrect data or go metastable

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Key idea of glitch-free clock gating

👉 Latch the enable signal only when the clock is in its inactive phase

Then use the latched enable to gate the clock.

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Standard glitch-free clock gating structure

For positive-edge triggered flip-flops

Components:

1. Level-sensitive latch (transparent when clk = 0)

2. AND gate

          enable

             |

             v

        +-----------+

        |   LATCH   |  (transparent when clk = 0)

        +-----------+

             |

             v

clk -----> AND ----------------> gated_clk

Operation:

• When clk = 0:

enable can safely change → latch updates

• When clk = 1:

latch holds its value → no glitch

• AND gate ensures clock passes only when latched enable = 1

⸻

RTL example (synthesizable, CGC-friendly)

module clock_gating (

    input  wire clk,

    input  wire enable,

    output wire gated_clk

);

reg enable_latched;

always @(clk or enable) begin

    if (!clk)

        enable_latched <= enable;

end

assign gated_clk = clk & enable_latched;

endmodule

⚠️ Note:

This style is recognized by synthesis tools and mapped to a standard clock gating cell from the library.

⸻

Integrated Clock Gating (ICG) Cells

In real ASIC flows, designers do not code gates manually.

Libraries provide ICG cells with:

• Built-in latch

• AND/OR logic

• Test enable (scan_enable)

• Low skew and low insertion delay

Typical ICG ports:

• CLK – input clock

• EN – functional enable

• SE – scan enable (forces clock ON during test)

• GCLK – gated clock output

⸻

With scan/test support

effective_enable = EN | SE

This ensures clocks are not blocked during:

• Scan shift

• ATPG

• DFT testing

⸻

Best practices

✅ Use library-provided ICG cells

✅ Place CGCs close to clock source

✅ Avoid gating clocks with combinational logic

✅ Ensure enable is synchronous to clock domain

✅ Use clock gating checks in STA tools

❌ Never gate clocks manually with AND/OR gates in final RTL

⸻

FPGA vs ASIC note

• ASIC: Clock gating is common and recommended

• FPGA: Avoid clock gating; use clock enable (CE) instead

⸻

Summary

Aspect Glitch-Free Clock Gating

Glitch risk Eliminated

Power saving High

Uses latch Yes

ASIC friendly Yes

DFT support Yes