UPF: Power Switch details — Power Switch in UPF (Unified Power Format) is used to control power gating (turning a power domain ON/OFF) to save leakage power in low-power VLSI designs.
UPF • LOW POWER
What is a Power Switch?
A power switch represents a set of header (PMOS) or footer (NMOS) transistors that connect/disconnect a power domain using enable/control signals—allowing blocks to be shut down during idle mode.
A power switch represents a set of header (PMOS) or footer (NMOS) transistors that connect/disconnect a power domain using enable/control signals—allowing blocks to be shut down during idle mode.
Why a Power Switch is needed
- Reduce leakage power
- Enable power-gated domains (power islands)
- Essential for mobile / low-power SoC designs
Where it is used
- VDD → Power-gated domain (header switch)
- Power-gated domain → VSS (footer switch)
Key UPF elements involved
create_power_domaincreate_supply_portcreate_supply_netcreate_power_switchset_domain_supply_net
Simple UPF Power Switch example
create_power_domain PD_CORE
create_supply_port VDD
create_supply_port VSS
create_supply_net VDD
create_supply_net VSS
connect_supply_net VDD -ports VDD
connect_supply_net VSS -ports VSS
create_power_switch PSW_CORE \
-domain PD_CORE \
-input_supply_port {VDD VDD} \
-output_supply_port {VDD_SW VDD} \
-control_port {PS_EN} \
-on_state {ON PS_EN}Meaning
- PSW_CORE → Power switch name
- VDD → VDD_SW → Switched power
- PS_EN → Enable signal
- When PS_EN = 1 → Power ON
- When PS_EN = 0 → Power OFF
Header vs Footer switch
| Type | Transistor | Position | Common use |
|---|---|---|---|
| Header | PMOS | Between VDD & block | Low noise |
| Footer | NMOS | Between block & GND | Area efficient |
Power switch with isolation & retention (typical flow)
- Power switch OFF
- Isolation enabled
- State retained (if needed)
- Power switch ON
- De-isolation
Real-world SoC usage
- CPU core sleep mode
- GPU power islands
- Peripheral shutdown blocks
Timing-safe power-up sequence (UPF)
This sequence avoids X-propagation, crowbar current, and timing violations during wake-up.
Power-Up Order (Recommended)
Power-Up Order (Recommended)
- Keep Isolation ON (clamp outputs to a known value)
- Enable Power Switch (ramp-up)
- Wait for Power Good (PG)
- Restore Retention Registers
- Release Reset
- Enable Clock
- Disable Isolation
set_isolation ISO_CORE -domain PD_CORE -clamp_value 0
# Enable power switch
# PS_EN = 1
wait (PWR_GOOD == 1);
set_retention_control RET_CORE -restore_signal RET_RESTORE
# Release reset
# RESET_N = 1
# Enable clock
# CLK_EN = 1
set_isolation_control ISO_CORE -isolation_signal ISO_EN -deassert
Golden Rule (Interview Favorite):
Isolation ON → Power ON → Power Good → Retention Restore → Reset Release → Clock ON → Isolation OFF
Isolation ON → Power ON → Power Good → Retention Restore → Reset Release → Clock ON → Isolation OFF
What happens if sequence is wrong?
| Mistake | Result |
|---|---|
| Isolation OFF before power | X-propagation |
| Clock ON before power | Short-circuit current |
| Reset before power good | Unknown state |
| No PG wait | Timing failures |
UPF Interview Questions & Answers
Q1. What is a power switch in UPF?
Ans: A power switch models header/footer transistors used to connect or disconnect power to a domain for leakage reduction.
Q2. Why is isolation required during power-up?
Ans: To prevent unknown (X) values from propagating from powered-off domains into active logic.
Q3. What is Power-Good (PG) signal?
Ans: A signal indicating that the supply voltage has reached a stable, safe operating level.
Q4. Difference between isolation and retention?
| Isolation | Retention |
|---|---|
| Protects outputs | Preserves internal state |
| Mandatory | Optional |
| Active when power OFF | Active before power OFF |
Q5. Why clocks are enabled last?
Ans: To prevent spurious switching and timing violations during unstable power.
Q6. What is inrush current and how do you avoid it?
Ans: Sudden current surge during power-up; avoided using staggered power switches or ramp-controlled enable.
Q7. Header vs Footer power switch?
| Header | Footer |
|---|---|
| PMOS | NMOS |
| Low noise | Area efficient |
| Near VDD | Near GND |
Q8. What happens if isolation is forgotten in UPF?
Ans: Functional simulation may pass, but gate-level simulation shows X-propagation and silicon failure.
Q9. Can a power-gated domain be clocked?
Ans: No. Clock must be gated OFF before power OFF and enabled only after power-up stabilization.
Q10. What checks ensure timing-safe power-up?
Ans:
- Power-aware STA
- UPF consistency checks
- PG signal timing validation
- Isolation/retention sequencing verification
“A timing-safe power-up ensures isolation first, stable power next, state restore, then clocks—never the other way around.”
