UPF : Power Switch details :
Power Switch in UPF (Unified Power Format) is used to control power gating—i.e., turning a power domain ON or OFF to save leakage power in low-power VLSI designs.
What is a Power Switch?
A power switch represents a set of header (PMOS) or footer (NMOS) transistors that:
• Connect or disconnect a power domain
• Are controlled by enable signals
• Allow blocks to be shut down during idle mode
Why Power Switch is Needed
• Reduce leakage power
• Enable power-gated domains
• Essential for mobile / low-power SoC designs
Where Power Switch is Used
• Between:
• VDD → Power-gated domain (header switch)
• Power-gated domain → VSS (footer switch)
Key UPF Elements Involved
• create_power_domain
• create_supply_port
• create_supply_net
• create_power_switch
• set_domain_supply_net
Simple UPF Power Switch Example :
-----------------
create_power_domain PD_CORE
create_supply_port VDD
create_supply_port VSS
create_supply_net VDD
create_supply_net VSS
connect_supply_net VDD -ports VDD
connect_supply_net VSS -ports VSS
create_power_switch PSW_CORE \
-domain PD_CORE \
-input_supply_port {VDD VDD} \
-output_supply_port {VDD_SW VDD} \
-control_port {PS_EN} \
-on_state {ON PS_EN}
-----------------
Meaning:
• PSW_CORE → Power switch name
• VDD → VDD_SW → Switched power
• PS_EN → Enable signal
• When PS_EN = 1 → Power ON
• When PS_EN = 0 → Power OFF
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Header vs Footer Switch
Type Transistor Position Common Use
Header PMOS Between VDD & block Low noise
Footer NMOS Between block & GND Area efficient
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Power Switch with Isolation & Retention (Typical Flow)
1. Power switch OFF
2. Isolation enabled
3. State retained (if needed)
4. Power switch ON
5. De-isolation
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Real-World SoC Usage
• CPU core sleep mode
• GPU power islands
• Peripheral shutdown blocks
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Timing-Safe Power-Up Sequence (UPF)
This sequence avoids X-propagation, crowbar current, and timing violations during wake-up.
🔌 Power-Up Order (Recommended)
1️⃣ Keep Isolation ON
• Prevents unknown values from propagating
• Outputs are clamped to a known value (0 or 1)
set_isolation ISO_CORE -domain PD_CORE -clamp_value 0
2️⃣ Enable Power Switch (Ramp-Up)
• Gradual power ramp avoids IR-drop & inrush current
• Controlled by PS_EN
PS_EN = 1
⏱ Wait until VDD reaches stable level
3️⃣ Wait for Power Good (PG)
• Power must be stable before logic wakes up
• Implemented via analog or digital PG signal
wait (PWR_GOOD == 1);
4️⃣ Restore Retention Registers
• Restores saved state
• Done before clocks are released
set_retention_control RET_CORE -restore_signal RET_RESTORE
5️⃣ Release Reset
• Reset ensures known startup state
• Must occur after power + retention restore
RESET_N = 1;
6️⃣ Enable Clock
• Clock last to avoid spurious switching
• Prevents metastability
CLK_EN = 1;
7️⃣ Disable Isolation
• Domain now fully functional
set_isolation_control ISO_CORE -isolation_signal ISO_EN -deassert
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📌 Golden Rule (Interview Favorite)
Isolation ON → Power ON → Power Good → Retention Restore → Reset Release → Clock ON → Isolation OFF
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⚠️ What Happens If Sequence Is Wrong?
Mistake Result
Isolation OFF before power X-propagation
Clock ON before power Short-circuit current
Reset before power good Unknown state
No PG wait Timing failures
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UPF Interview Questions & Answers
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Q1. What is a power switch in UPF?
Ans: A power switch models header/footer transistors used to connect or disconnect power to a domain for leakage reduction.
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Q2. Why is isolation required during power-up?
Ans: To prevent unknown (X) values from propagating from powered-off domains into active logic.
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Q3. What is Power-Good (PG) signal?
Ans: A signal indicating that the supply voltage has reached a stable, safe operating level.
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Q4. Difference between isolation and retention?
Isolation Retention
Protects outputs Preserves internal state
Mandatory Optional
Active when power OFF Active before power OFF
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Q5. Why clocks are enabled last?
Ans: To prevent spurious switching and timing violations during unstable power.
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Q6. What is inrush current and how do you avoid it?
Ans: Sudden current surge during power-up; avoided using staggered power switches or ramp-controlled enable.
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Q7. Header vs Footer power switch?
Header Footer
PMOS NMOS
Low noise Area efficient
Near VDD Near GND
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Q8. What happens if isolation is forgotten in UPF?
Ans: Functional simulation may pass, but gate-level simulation shows X-propagation and silicon failure.
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Q9. Can a power-gated domain be clocked?
Ans: No. Clock must be gated OFF before power OFF and enabled only after power-up stabilization.
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Q10. What checks ensure timing-safe power-up?
Ans:
• Power-aware STA
• UPF consistency checks
• PG signal timing validation
• Isolation/retention sequencing verification
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“A timing-safe power-up ensures isolation first, stable power next, state restore, then clocks—never the other way around.”
UPF : Details on Level Shifter
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