Convergence , divergence and re-convergence

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Now a days , multiple clocks in a system are common due to increasing frequency and complexity. A CDC check is a must check on the design before tapping out as any CDC violation may be fatal and could be a cause of chip failure.

In one of my blog I have explained the basic technique used in synchronization , here I will more focus on few design rules related to convergence , divergence and re-convergence.

Convergence 

Convergence here is, two signals coming from different path and getting used in one combination logic gate and output of gate is getting synchronized in destination clock domain , please see the below figure.

Here the issue could be , a glitch may propagated into receiving clock domain , which can sample and cause a functional issue.

CDC tool will detect this kind of issue and will give it in report. Designer should analyze it and fix it properly. As a standard rule for CDC, before synchronizing the signal , there should not be any combinational logic , signal going into sync cell should be output of a flop otherwise tool will issue warning for that , which will be described later.



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Divergence 

Some time a good design style lead to chip failure .. but we are safe as this is not related to divergence :)
Divergence is , when a control signal synchronized at different places and output of those synchronizers used in combinational logic. CDC tool will report as divergence issue , here the issue could be a glitch because of different path delay ,  This may lead to a functional error in a chip.

Please see below figure  -

Here data_en_sync and addr_en_sync may have different path delay.
Other example of divergence is , using meta stable signal. look into below figure.

This is most common mistake made by designers, they used to put sync flop but they might see this violation reported by tool.. the reason is , if signal coming from combinational logic ,tool think the second flop of sync cell is actually first flop of sync cell  , and then output of sync cell is used in other logic , tool may issue this warning.

It is always better to flop the signal first and then synchronized it in destination clock domain.

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Re-convergence 

Re-convergence is , different signals coming through sync cell is getting used in some logic , a simple form of this is , synchronization of the individual bits of a bus  .. due to this there could be skew in data arrival and there could be a chance one sync cell capturing data a bit late which may cause 1 cycle delay. In this case, arriving data will no more valid and called as corrupted data.


Below is the figure - 

This is all about the convergence, divergence, re-convergence ..

Thanks for reading it. 

Rahul J

Pos n Neg edge detector

Circuit diagram for posedge detector and negedge detector :

Below is the verilog code for positive detector and negative detector -

I have developed the testbench also , all in verilog :)

module pos_edge_detect ( clk, nrst, din, dout);
input clk;
input nrst;
input din;
output dout;

reg d_ff;

always @(posedge clk or negedge nrst) begin
  if(!nrst)
     d_ff <= 1'b0;
  else
    d_ff <= din;
end

// Positive edge detection
assign dout = din && (d_ff ^ din);

// Negative edge detection
// assign dout = (~din) && (d_ff ^ din);


endmodule

module tb1;

  reg clk;
  reg reset;
  reg [4:0] count;

  pos_edge_detect dut (.clk(clk),
  .nrst(reset),
  .din(count[0])
  );




  initial begin
    clk = 0 ;
    reset = 0;
    count = 0 ;
  end

  always #5 clk <= ~clk;

  initial begin
    #100;
    reset = 1;
  end

  always @(posedge clk)
    count <= count + 3 + count[2] ;
 
    initial begin
      $dumpfile("temp.vcd");
      $dumpvars();
      #3000;
      $finish;
    end
 

endmodule

SDC File - A Sample file for Synthesis

Design Specification 
A counter having 2 input clocks, clk_a running at 100 MHz and clk_B running at  200MHz.
there are clock divider for clk_A in design.
Counter having inputs clk_A , clk_B , reset, count_start1 ,count_start2  and output count_val
1.count_start1 clocking with clk_A
2.count_start2 clocking with clk_B
3.count_val clocking with clk_A
4.reset is synchronous and clocked with clk_A

below is the sample SDC file - counter.sdc

At the top of SDC , below optional commands

# create source clock
create_clock -name clka -period 10 [get_ports clk_A]
create_clock  -name clkb -period 5   [get_ports clk_B]

#create generated clock
create_generate_clock -divide_by 2 -source [get_ports clk_A] -name clk_DIV_A  [get_pins <pin_name>]

# set clock uncertainty  (setup) , here 10% or more depend on clock frequency and technology library
set_clock_uncertainty -setup <10% of clk_A> [get_clocks clk_A]
set_clock_uncertainty -setup <10% of clk_B> [get_clocks clk_B ]

#set clock uncertainty (hold) , Hold doesn't depend on clock frequency.
# $hold_margin - 50 ps
set_clock_uncertainty -hold  $hold_margin   [all_clocks]

## set clock latency if required

# declare false path between clk_A and clk_B
set_clock_groups -logically_exclusive [get_clocks clk_A clk_B]
or set_false_path -from clk_A -to clk_B
    set_false_path -from clk_B -to clk_A

## Declare input delays and output delays on ports
set_input_delay -clock clk_A -max {0.5*clk_A period} [get_ports count_start1 ]
set_input_delay -clock clk_A min 0 [get_ports count_start1]

set_input_delay -clock clk_B -max {0.5*clk_A period} [get_ports count_start2 ]
set_input_delay -clock clk_B min 0 [get_ports count_start2]

set_output_delay -clock clk_A -max {0.5*clk_A period} [get_ports count_val ]
set_output_delay -clock clk_A min 0 [get_ports count_val]

#declare multicycle paths
set_multicycle_path   <declare multicycle path if any in design>


##Below are the constraints helps to setup the environments

set_case_analysis 0 [get_pins counter/heir_a/sel_a]

set_driving_cell -lib_cell BUFX9 [all_inputs]

set_fanout_load 8 [all_outputs]

set_load 50  [all_outputs]   ## set the value of capacitive load on pin or net in design

# set the specified ports/pins at logic zero or logic one (this is similar to set_case_analysis)
set_logic_zero [get_ports <>]
set_logic_one  [get_pins <> ]

set_max_area  ## if there is any area specific requirement
set_max_capacitance  0.1 [all_outputs]
set_max_transition  0.2  [all_pins]  ## specify the max transition time on pins or ports
set_port_fanout_number  5 [get_ports <PORT>]  ## set maximum fanout of a port

commands which I have not defined in above sdc -
set_min_delay -from PATH_A -to PATH_B 1 ## set minimum delay 1 ns from path A to B
set_max_delay -from PATH_A -to PATH_B 2   ## set maximum delay 2 ns from path A to B

There are many other commands which may be used in design but those are more specific to the requirement, design implementation , and technology specific. Above all sdc commands are generic commands.

Let me know if there are anything I missed here or any question , please feel free to ask.

Thanks
Rahul Jain

Verilog - Reserved KeyWords

always         starts an  always begin ... end  sequential code block
and            gate primitive, and
assign         parallel continuous assignment
automatic      a function attribute, basically reentrant and recursive
begin          starts a block that ends with  end (no semicolon)
buf            gate primitive, buffer
bufif0         gate primitive, buffer if control==0
bufif1         gate primitive, buffer if control==1
case           starts a case statement
casex          starts a case statement where x matches
casez          starts a case statement where z matches
cell           library, cell identifier, in configuration
cmos           switch primitive, cmos
config         starts a configuration
deassign       stops the corresponding  assign  from accepting new values
default        optional last clause in a case statement
defparam       used to over-ride parameter values
design         top level module, in configuration
disable        a task or block
edge           edge control specifier
else           execute if no previous clause was true
end            end of a block, paired with a begin
endcase        end of a case statement
endconfig      end of a configuration
endfunction    end of a function definition
endgenerate    end of a generate
endmodule      end of a module definition
endprimitive   end of a primitive definition
endspecify     end of a specify
endtable       end of a table definition
endtask        end of a task definition
event          data type
for            starts a for statement
force          starts net or variable assignment
forever        starts a loop statement
fork           begin parallel execution of sequential code
function       starts a function definition
generate       starts a generate block
genvar         defines a generate variable
highz0         drive strength 0
highz1         drive strength 0
if             starts an  if  statement, if(condition) ...
ifnone         state dependent path declaration
incdir         file path for library
include        include file specification
initial        starts an initial begin ... end sequential block
inout          declares a port name to be both input and output
input          declares a port name to be input
instance       specify instance name, in configuration
integer        variable data type, 32 bit integer
join           end of a parallel fork
large          charge strength, 4, of trireg
liblist        library search order for modules, in configuration
library        location of modules, libraries and files
localparam     starts a local parameter statement, not over-ridden
macromodule    same as module with possibly extra meanings  
medium         charge strength, 2, of trireg
module         begin a module definition, also called a cell or component
nand           gate primitive, nand
negedge        event expression, negative edge
nmos           switch primitive, nmos
nor            gate primitive, nor
noshowcancelledno report trailing edge precedes leading edge, in specify
not            gate primitive, not
notif0         gate primitive, not if control==0
notif1         gate primitive, not if control==1
or             gate primitive, or
output         declares a port name to be an output
parameter      starts a parameter statement
pmos           switch primitive, pmos
posedge        event expression, positive edge
primitive      starts the definition of a primitive module
pull0          drive strength 5
pull1          drive strength 5
pulldown       gate primitive
pullup         gate primitive
pulsestyle_oneventglitch detection, in specify
pulsestyle_ondetectglitch detection, immediate change to x, in specify
remos          switch primitive, remos
real           variable data type, implementation defined floating point
realtime       variable data type, floating point time
reg            variable data type, starts a declaration of name(s)
release        release a forced net or variable assignment
repeat         starts a loop statement
rnmos          switch primitive, rnmos
rpmos          switch primitive, rpmos
rtran          bidirectional switch primitive, rtran
rtranif0       bidirectional switch primitive, rtranif0
rtranif1       bidirectional switch primitive, rtranif1
scalared       property of a vector type
showcancelled  report trailing edge precedes leading edge, in specify
signed         type modifier, reg signed
small          charge strength, 1,  of trireg
specify        starts a specify block
specparam      starts a parameter statement for timing delays
strong0        drive strength 6
strong1        drive strength 6
supply0        net data type, and drive strength 7
supply1        net data type, and drive strength 7
table          start a table definition in a primitive
task           starts a task definition
time           variable data type, 64 bit integer
tran           bidirectional switch primitive, tran
tranif0        bidirectional switch primitive, tranif0
tranif1        bidirectional switch primitive, tranif1
tri            net data type
tri0           net data type, connected to VSS
tri1           net data type, connected to VDD
triand         net data type, tri state wired and
trior          net data type, tri state wired or
trireg         register data type associates capacitance to the net
unsigned       type modifier, unsigned
use            library, cell identifier, in configuration
vectored       property of a vector type
wait           starts a wait statement
wand           net data type, wired and
weak0          drive strength 3
weak1          drive strength 3
while          starts a sequential looping statement, while(condition) 
wire           net data type, a basic wire connection
wor            net data type, wired or
xnor           gate primitive, xnor not of exclusive or
xor            gate primitive, xor exclusive or

Verilog Operators

Verilog HDL operators are same as in C language.

{}   - concatenation 

usage -
reg ab;
reg [1:0] cd ;
reg  [2:0] z ;

always @(*) begin
   z = {cd, ab} ;
end

{3{A} } //  this is equivalent to { A, A, A}
{2 {X, Y}, Z} is equivalent to  {X, Y, X, Y , Z}

+, - , * , /   - arithmetic 

usage -
used in conventional way ..  A = B + C ;

if B and C is 4 -bit , then A should be 5-bit (sum + carry)


%   --  modulus

example - 10 %3  will give remainder 1

> >= < <=    ---  relational

a<b      a less than b
a>b      a greater than b
a<=b    a less than or equal to b

a>=b    a greater than or equal to b

!    --  logical negation

!a  -  invert of a

&&  -- logical and
This is not a bit wise logical AND , bit wise is &

||    --  logical or
This is not a bit wise OR , bit wise is |

==     ---    logical equality
example
a == b a equal to b, result may be unknown


!=      ---   logical inequality
example
a != b a not equal to b, result may be unknown

=== case equality
example
a === b a equal to b, including x and z

!== case inequality
example
a !== b a not equal to b, including x and z

~ bit-wise negation

& bit-wise and

| bit-wise inclusive or

^ bit-wise exclusive or

^~ or ~^ bit-wise equivalence

<<   left shift

>>   right shift


?: conditional


Verilog having syntax restriction for using space , please see below for details.

X & &Y    and X && Y  is  not same ,
X | |Y  and  X |  |Y  is not same.

It is always better to use parenthesis for nested kind of operations.

I think those are the operators which we used normally in RTL coding , there are other operators like string manipulation, but those we don't use in RTL coding.

Please let me know If I missed something here.

NEXT

Pages which you would like to visit -
Verilog Overview
Brain refreshment through Verilog 

Thanks
Rahul J