Verilog Design Style

Verilog HDL allow users to go for design either bottom up or top down.

Bottom up - 
The traditional method of electronic design is bottom-up. Each design is performed at the gate-level using the standard gates (refer to the Digital Section for more details). With the increasing complexity of new designs this approach is nearly impossible to maintain.


Top Down -
The desired design-style of all designers is the top-down one. A real top-down design allows early testing, easy change of different technologies, a structured system design and offers many other advantages.

With increasing complexity in the design and increasing gate count , it is impossible to keep one pure approach through out the development of a design , people are following a mix of both approach.

From my experience , First I used Top down approach and defined all the interface at top level and  then define the sub block in the design. Once architecture is finalize at broad level then one can start exploring the individual blocks and those blocks can be designed with Bottom up approach.

It is a common approach to build the logic, you need to prepare micro-architecture and architecture document before coding. Coding you can do either with verilog or with VHDL.

Verilog - Statements

Parallel statement -    

fork ...... join

Conditional statement - 

if ..... else 

if .... else if .... else 

case 

casez

casex

Looping statement 

forever 

for ( ) 

repeat () 

while () 

Continuous Assignment  

wire abc = 5'd10 ;

assign abc = 5'd10 ; 

assign a = b ; 

Procedural Assignment 

initial 

always 

task

function

Blocking Assignment 

a = b ;

b = c ; 

c = a ; 

Non-Blocking Assignment 

a <= b ;

b <= c ;

c <= a ;

Verilog - Data Types

Verilog HDL consists of 4 basic values -
0 - Logic zero
1 - Logic one
x - unknown value
z -high-impedance state

value z and x are same, notable exception are the primitives which can pass the z value.

Nets and Registers 
The net data types represent the physical connections, a net does not store a value (except trireg net).
Register type will store the value from assignment.

Declaring reg and net types -

reg [N-1:0] <reg_name1> , <reg_name2> ;

declaring N-bit register named reg_name1 and reg_name2

wire [N-1:0] <wire_name1> , <wire_name2>;

declaring N-bit wire named wire_name1 and wire_name2

tri [N-1:0] tri_name ;
A tri state tri_name signal with N-bit

One can declare integer , time , real type of variables.

Declaration of memory -

reg [3:0] mem [4:0] ;

This will create memory of 5 registers of 4-bit each.


Parameters 

Parameters are not reg type or wire type, all parameter declaration is a constant.
syntax to declare parameter -
parameter abc = 1;
parameter x =10, y = 12;
parameter z = expression (abc) ;   // abc should be a constant value

NEXT

Pages which you would like to visit -
Verilog Overview
Brain refreshment through Verilog 

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Rahul Jain

NAND gate using Mux

Draw a  2 input NAND gate using 2:1 mux

AND , OR gate using 2:1 Mux

Reset Removal and Recovery time

These are timing checks for asynchronous signals similar to the setup and hold checks.


Reset Recovery time is the minimum amount of time required between the release of an asynchronous signal from the active state to the next active clock edge.


Example: The time between the reset and clock transitions for a flip-flop. If the active edge occurs too soon after the release of the reset, the state of the flip-flop can be unknown.


Reset Removal time specifies the minimum amount of time between an active clock edge and the release of an asynchronous control signal.


The following diagram illustrates recovery and removal times for an active low reset signal (RESET_N) and positive-edge triggered CLOCK

So how do we resolve reset removal and recovery timing violation ? 

This is one of the reason for re-tapeout of SoC. 

Other useful links -

How To debug a simulation 

Refreshing your brain with Verilog 

Digital Design of Hybrid Memory Cube

Correct way of  Digital design RTL Coding

Clock Gating Circuits

Digital Design Interview Question

Knowledge on Verification

Simulator Execution for Blocking and non-blocking statement 

Low Power Design and Verification

Low power design is not a new area, but it was not that much important as it is now.
Semiconductor market trend is very fast changing , and it is a challenge to face and ready with new technology.

The low power design , these days it is important because technology is now getting saturated with 28 nm , if you go below of that then device will be more costlier. So now in coming days people will move into low power design, the other reason is , as you go from 160um to 28um,  power dissipation was not much on 90 or above um technology, but as technology moving into more advanced, power dissipation going higher and higher.

Other reason is , these days we are using battery operated device like cellphone, tablet, laptop, etc , one of the major factor on these device is battery , people want long life for battery  and a good low power design can give you long life battery

Below is the graph showing power trend with respect to time , as we are moving from 2006 to 2020, static power dissipation is more and more , static power dissipation happens when device is in idle state , which means , now a days there are many module which stay ideal most of time.

In CMOS , below is the chart for power consumption -

So .. Where does the power go ?

In SoC design , total power consists of dynamic power and static power.
Dynamic power dissipation is due to signal activity , when signal changing value from 1 to 0 or 0 to 1, there will be power dissipation.
Static power dissipation is due to leakage power and it happen when device is in ideal state.

Dynamic Power Dissipation

Below is the equation to calculate the dynamic power.

                           P(dyn)  =  C*Vdd*Vdd*f
where ..
f -  frequency
Vdd-  Voltage
C - effective capacitance

Dynamic Power depend on clock frequency , power supply , switching activity , transistor width ,length , etc

Static Power Dissipation 
Static power dissipation is due to leakage current. below is a pictorial comparison between dynamic power and static power.

There are few technique used to save power in design, few of them I have mentioned below.

Clock Gating

1. Clock trees are a large source of dynamic power.
2. Clock gating can occur at any level  in design. 
3. Try to put clock gating circuit near to clock source , this will save a significant amount of power. 

Operand Isolation

1. Datapath computation elements are sampled only periodically.
2. Adding one enable signal and control sampling with enable signal.
3. Whenever enable is inactive , datapath inputs can be forced to constant value, this will result in saving dynamic power.

Multi Vth

1. Multiple voltage threshold optimization utilizes gates with different threshold to optimize for power, timing and area constraint. 
2. A good synthesis tool should be able to mix available multi threshold library cells to meet speed and area constraint with low power dissipation.

MSV ( Multi Supply Voltage)

1. Multi-supply voltage techniques operate different blocks at different voltages.
2. Running at a lower voltage reduces power consumption, but at the expense of speed. 
3. Designers use different supply voltages for different parts of the chip based on their performance requirements.
4. MSV implementation is key to reducing power since lowering the voltage has a squared effect on active power consumption.
5. MSV techniques require level shifters on signals that go from one voltage level to another. 
6. Without level shifters, signals that cross voltage levels will not be sampled correctly.

Dynamic Voltage and frequency scaling 

Supply voltage plays a major role power dissipation as it used in calculation in dynamic power as well as leakage power dissipation. Reducing voltage supply will save a lot of power but it will make design work at lower frequency. If you reduced voltage , then this will result in increment of combinational/sequencial delays. Also if design is working at low frequency then power dissipation will be less. This is dynamic power management and may be hardware/firmware control power supply and frequency of design, depends on implementation.

Power Shut-Off  (PSO)

1. One of the most effective technique – called power gating.
2. Switch off the power to parts of chips when blocks are not in use.
3. it can eliminate up to 96% of leakage current.
4. A specific power sequence is needed which includes isolation on signals from the power down domain.

Isolation 

1. Isolation logic is typically used at the output of a powered-down block to prevent floating or unpowered signals from propagating from powered-down blocks.
2. The outputs of blocks being powered down need to be isolated before power can be switched off; and they need to remain isolated until after the block has been fully powered up. Isolation cells are placed between two power domains and are typically connected from domains powered off to domains that are still powered up.

State Retention 

1. To speed-up recovery, state retention power gating flops can be used. 
2. Those flops retain their state while the power is off. 
3. Area of verification is to checking the library specific requirement should be satisfied and flops actually retaining their state.

Memory Splitting

1. In many systems, the memory capacity is designed for peak usage. During normal system activity, only a portion of memory is actually used at any given time.
2. In many cases, it is possible to divide the memory into two or more sections and selectively power down unused section of memory.

Low Power Verification 

Low power verification is having extra effort in verification to verify low power design , there are few area which we can not verify in simulation but there are tools available in market. 

In simulation perspective, below features can be verified - 

1. Power up/Power down sequence 
2. Assertions on boundary 
3. Isolation/Retention cells verification
4. Hardware-Software deadlock 
5. Power-on Reset/ Bring up

UPF (Unified Power Format)  - 

UPF plays a major role in low power design , this is a TCL based script which having information about the power intent of design and specify the power domain.  This file is similar to SDC file , except SDC has timing information and UPF has power related information but syntax totally different in SDC and UPF.  If there are multi supply voltage used in design, then designer will have to create UPF file and put that information into file.

Few points about UPF -

1. IEEE 1801 standard format
2. Extension of Tcl tool command language 
3. Defined separately from HDL
4. Enables early verification 
5. Drive verification and implementation from RTL to layout 

Common command used in UPF 

• create_power_domain
• set_isolation
• set_level_shifter
• set_retention
• create_supply_port
• create_supply_net
• create_power_switch
• connect_supply_net
• add_port_state
• create_pst
• add_ast_state .. etc 

For more detail on UPF , visit below page .. 

UPF (Unified Power Format)

Other Topics -
Contents
Refreshing your brain with Verilog 
Digital Design of Hybrid Memory Cube
Correct way of  Digital design RTL Coding
Clock Gating Circuits
Digital Design Interview Question
Knowledge on Verification
How To debug a simulation
Retention cells 

More are yet to come , all comments and suggestions are welcome and will help to put information here.  

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How simulator executes blocking and non-blocking statement in Verilog

We all know that there are blocking statements and non-blocking statements ,  If I ask what is blocking and what is non-blocking , the first answer I used to get is , blocking used in combinational circuits and non-blocking used in sequential circuit.

People makes mistake while saying above statement , it's not definition.

below is the definition of blocking statement -

A blocking procedural assignment statement must be executed before the execution of next statement in a sequential block. But a blocking procedural assignment statement does not prevent the execution of statement that follow it in parallel block.

What does it mean ..  ??

In simple way , in blocking statement , simulation tool evaluates RHS and assigned it to LHS before moving to next statement.
but when you are using fork...join  , this is parallel execution and simulation tool will start evaluation of all statements in fork ...join with same time stamp.

If this question asked during interview, then don't make a mistake by saying "=" is blocking statement and "<=" is non-blocking statement.


Non-Blocking statement - 
The non-blocking procedural assignment allows you to schedule assignments without blocking the procedural flow. You can use the non-blocking procedural statement whenever you want to make several register assignments within the same time step without regard to order or dependence upon each other.

It means , in a procedural block, all non-blocking statement will executes at same time stamp , simulation tool will start evaluating all non-blocking statement at same time stamp but assignment will happen at the end of current time stamp.

Now, the question is , why do we say combinational logic uses blocking statement and sequential logic uses non-blocking statement ??

Imagine you have combinational logic , 2 AND gate connected back to back , if something happen on AND1 gate then after gate delay, assignment will happen on AND2 gate , and this event is not depend on any clock or other signal, its continuous assignment and  whenever AND1 gate input change , AND2 gate output will changed.

if you write this in non-blocking style, then this will not be correct and old value of AND2 gate will propagate to sequential circuit in simulation , but in actual hardware , correct value of AND2 gate will propagated.
So there is mismatch between simulation and actual hardware and to stop this, we follow the guideline which say combinational circuit should use blocking type of statement.

If you have used non-blocking type of statement in combinational logic, you must get lint warnings in log. Every designer should check lint log carefully.

How the simulator evaluates non-blocking procedural assignments

When the simulator encounters a non-blocking procedural assignment, the simulator evaluates and executes the non-blocking procedural assignment in two steps.
1. The simulator evaluates the right-hand side and schedules the assignment of the new value to take place at a time specified by a procedural timing control.
2. At the end of the time step, in which the given delay has expired or the appropriate event has taken place, the simulator executes the assignment by assigning the value to the left-hand side.


How the Simulator Processes Blocking and Non-Blocking Procedural Assignments

For each time slot during simulation, blocking and non-blocking procedural assignments are processed in the following way:
1. Evaluate the right-hand side of all assignment statements in the current time slot.
2. Execute all blocking procedural assignments. At the same time, all non-blocking procedural assignments are set aside for processing.
3. Execute all non-blocking procedural assignments that have no timing controls.
4. Check for procedures that have timing controls and execute if timing control is set for the current time unit.
5. Advance the simulation clock.

Very good article to understand more --
http://web.mit.edu/6.111/www/f2007/handouts/L06.pdf

Other Article -
Digital Design .... 

Posted by Rahul Jain , Technical Lead at Synapse Design, Bangalore

Verilog - Lexical Element

Lexical --  it means related to the language, here will describe in more detail about the lexical elements in verilog.

Convention Overview 

This is important because this will let you know how to use verilog construct in RTL coding. Verilog is not much high rule constraint based language ,but to use it , you need to know few basic thing mentioned below.

• operator
• whitespace
• comment
• number
• string
• identifier
• keyword

operator 

Operators are single, double or triple character sequence and used in expression.

Urinary operators appear to be left of their operand.
Binary operators appear between their operands.
A ternary operator has two operator character that separate three operands.

white space and comments 
white space can contain char like space, tab, newlines ,etc
comments , one line comment will start from  //
multiple line comments will start from /* and end with */

number
Constant number can be specified in decimal, hexadecimal, octal or binary format.

exp -
23   // decimal number
'b10101  // binary number
'd23   // decimal number
'hF3  // hex number
'o23 // octal number

This can be divided into sized and unsized number .. sized number will be like 5'h1F  // 5 -bit number

string 
string is a sequence of character enclosed by double quotes and all must be in a single line.
Verilog treats strings used as operand in expression and assignment as a sequence of 8-bit ASCII value.
string manipulation is also possible in verilog but all will be done after converting into ASCII value.

Will not go in much details as we normally don't use those in RTL coding.
Special character in string -

\n  - new line
\t  - tab charc
\\ \character
\" "character
%% %character

identifier 
first character must not be a digit or $ ; it can be a letter or an underscore
lowercase , uppercase letters are considered to be different.

Escaped Identifiers 
Escaped identifiers start with the backslash character (\) and provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal).


keyword 
Keywords are predefined non-escaped identifiers that are used to define the language construct.
Any keyword having escape character in starting , is not considered as Verilog Keyword.
system task includes in keywords.

Text Substitution 
For re-usability of RTL code , one can use `define in RTL and use Macro in RTL instead of constant number.
all define/parameter can be override or defined in a separate file which can used in configuration of design.

NEXT

For more information, visit below page.
Verilog - Compiler Directive

Verilog Overview main page -
Verilog Overview


Thanks for your time.

Verilog Overview

• Introduction
  
• Design Style
  
• Language description
  
  • Module
    
  • Lexical conventions
    
  • Data types
    
  • Operators
    
• Modeling Style
  
  • Gate Level Modeling
    
  • Data Flow modeling
    
  • Behavioral Modeling
    
• Other things in Verilog
  
• Simulation and testbench

• Refreshing your brain with Verilog