These are timing checks for asynchronous signals similar to the setup and hold checks.
Reset Recovery time is the minimum amount of time required between the release of an asynchronous signal from the active state to the next active clock edge.
Example: The time between the reset and clock transitions for a flip-flop. If the active edge occurs too soon after the release of the reset, the state of the flip-flop can be unknown.
Reset Removal time specifies the minimum amount of time between an active clock edge and the release of an asynchronous control signal.
The following diagram illustrates recovery and removal times for an active low reset signal (RESET_N) and positive-edge triggered CLOCK
So how do we resolve reset removal and recovery timing violation ?
This is one of the reason for re-tapeout of SoC.
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