Here we will discuss about the useful modeling techniques.
Procedural Continuous Assignments :
These are the statements which allow values to be driven continuously onto registers or nets.
Exp: assign and deassign
A simple example is the positive edge triggered D-flip-flop with asynchronous reset.
// ------------------------
//Author - Rahul Jain
// D-flipflop with Asynchronous Reset (active high)
module dff ( d, clk, reset, q ) ;
input d, clk, reset;
output q;
reg q ;
always @(posedge clk) begin
q = d ;
end
always @(reset) begin
if (reset)
assign q = 1'b0;
else
deassign q ;
end
endmodule
// ------------------------
Here in the example , we overrode the assignment on q and assign new values to them when reset goes high. The register "q" variable retain the continuously assigned value after the deassigned.
This is now a bad practice and we do not use it in RTL code, whereas We use the non-blocking statement in procedural statement.
Force and Release :
Ref : Verilog HDL ( Samir Palnitkar)
