How to Dump the Synchronizer Cell List in SpyGlass CDC
In complex multi-clock SoC designs, identifying, auditing, and validating all Clock Domain Crossing (CDC) synchronizer cells is a critical sign-off step. Relying on manual inspection is error-prone. Fortunately, Synopsys SpyGlass provides highly automated mechanisms to discover and dump a comprehensive list of all identified synchronizers into a structured report file.
However, since every ASIC or FPGA design handles clock domains differently, out-of-the-box settings may miss structural synchronizers or produce overly pessimistic violations. Fine-tuning your SpyGlass project setup is usually required to generate a clean, reliable structural report.
Custom Goals vs. Standard CDC Goals
To dump your synchronizer list, you have two primary implementation paths in your SpyGlass project file (.prj):
- Modify a standard goal: Append specific report and dump options directly to an existing CDC goal (like
cdc/cdc_verify_struct). - Define a custom goal: Create a dedicated, lightweight evaluation goal that runs only the rules required for tracking synchronizers. This saves significant compilation time during iterative debug cycles.
SpyGlass Project File Setup (Design1.prj)
# =========================================================================
# Custom Goal Definition for Synchronizer Discovery and Reporting
# =========================================================================
define_goal custom_sync_dump -policy {clock-reset} {
## Enable only the essential structural rules to discover data crossings
set_goal_option rules { Ac_unsync01 Ac_unsync02 Ac_sync01 Ac_sync02 }
## Configure output reports: SynchInfo captures the structural dump file
set_goal_option report { SynchInfo moresimple }
## Specify wildcards for the tool to recognize hardcoded or custom cells
set_parameter synchronize_cells "*sync1*, *sync2*"
set_parameter reset_synchronize_cells "*rst_sync*"
## Core control parameter to force detailed dump generation
set_parameter dump_sync_info detailed
## Optional Handling for Complex Topologies
set_parameter allow_combo_logic yes
set_parameter allow_merged_qualifier yes
## Pessimism Reduction & Advanced Analysis Controls
set_parameter enable_and_sync yes
set_parameter cdc_reduce_pessimism all
set_parameter strict_sync_check yes
set_parameter enable_debug_data yes
}
Key Parameter Breakdown Explained
To get the most out of your report, it helps to understand what these parameters instruct the underlying SpyGlass engine to do:
dump_sync_info detailed: The most crucial configuration line. This commands SpyGlass to populate theSynchInforeport with exact cell names, hierarchies, source domains, and destination domains.synchronize_cells&reset_synchronize_cells: Tells the structural engine which custom library cells or module design patterns represent valid synchronizers. Wildcards (*) are allowed.allow_combo_logic yes: Useful if your design features static multiplexers, clock-gating or configuration masking logic sitting right before the synchronizer flop. It prevents the tool from invalidating the crossing due to combinational logic.allow_merged_qualifier yes: Required when a control/data signal originates from different source elements before converging on a single synchronizer cell. It evaluates the crossing assuming the source components are quasi-static.cdc_reduce_pessimism all: Forces the tool to actively filter out redundant or false violations, ensuring only genuine clock domain crossings are analyzed and logged.
A Practical Example: Verilog Code vs. SpyGlass Parameters
Consider the following simple design snippet handling an asynchronous data bus bit crossing alongside an asynchronous reset tree:
// Data Path Synchronizer module data_sync1 ( input wire clk_b, input wire data_in_clka, output reg data_out_clkb ); reg sync_ff1; always @(posedge clk_b) begin sync_ff1 <= data_in_clka; data_out_clkb <= sync_ff1; end endmodule // Reset Path Synchronizer module rst_sync_macro ( input wire clk_b, input wire async_rst_n, output reg sync_rst_clkb_n ); reg rst_ff1; always @(posedge clk_b or negedge async_rst_n) begin if (!async_rst_n) begin rst_ff1 <= 1'b0; sync_rst_clkb_n <= 1'b0; end else begin rst_ff1 <= 1'b1; sync_rst_clkb_n <= rst_ff1; end end endmodule
How the parameters match this code:
- The instance of
data_sync1matches the*sync1*pattern inside thesynchronize_cellsparameter. - The instance of
rst_sync_macromatches the*rst_sync*pattern inside thereset_synchronize_cellsparameter. - When you run the
custom_sync_dumpgoal, SpyGlass will capture these matched instances along with their source clock metadata and dump them safely into the generatedSynchInfofile inside your workspace directory.
Using this structured method guarantees your design review team has a verifiable, single source of truth for all cross-domain paths in the SoC.
Hope this information is useful to you! Comment or email me if you need any support on setting up custom goals or handling tricky CDC patterns in SpyGlass.
