Here is the updated HTML with a visual **AXI Read Transaction Timeline** added to Q4. It uses pure CSS/SVG for crisp graphics that work well on blog pages. ```html AXI / AHB Interview Guide

Interview Prep • AXI / AHB / SVA

Chip Design Expert

AXI & AHB Interview Guide

A polished, ready-to-post set of 15 common AXI/AMBA interview questions with crisp answers, a comparison table, a visual read-transaction timeline, and a SystemVerilog assertion example.

Jump to Q1 ↓ Q4 Read Timeline → SVA Example → Table of Contents →

Q1 AHB vs AXI Q2 What is AXI-Lite? Q3 Five AXI features Q4 AXI read transaction Q5 Data interleaving Q6 Out-of-order support Q7 Outstanding addresses Q8 Data integrity Q9 SVA handshake Q10 OoO vs interleaving Q11 Flow control Q12 LAST signal Q13 Bursts vs transfers Q14 Max transfer size Q15 Strobing (WSTRB)

Difference between AHB and AXI?

AHB (Advanced High-performance Bus) and AXI (Advanced eXtensible Interface) are both core interconnect protocols within the ARM AMBA specification, but AXI delivers significantly higher throughput and bandwidth by employing a channel-based architecture instead of a shared-bus structure. AHB is ideal for medium-performance, low-latency system components, while AXI is designed for high-performance, high-frequency SoC designs.

Feature	AHB (AMBA 2 / AHB-Lite)	AXI (AMBA 3 / AXI4 / AXI5)
Architecture Type	Shared, multiplexed bus structure.	Independent, channel-based topology.
Bus Channels	Shared address/data lines for read and write.	5 independent channels (AW, W, B, AR, R).
Read/Write Concurrency	Half-duplex.	Full-duplex (simultaneous read and write).
Outstanding Transactions	Not natively supported.	Supported natively via transaction IDs.
Out-of-Order Execution	In-order processing only.	Out-of-order data completion via ID tags.
Burst Support	Incrementing and wrapping bursts.	FIXED, INCR, and WRAP burst types.
Maximum Burst Length	Up to 16 beats.	Up to 256 beats per burst (AXI4).
Design Complexity	Moderate; simpler control logic.	High; complex interconnect matrices.

What is AXI-Lite?

AXI-Lite is a simplified, lightweight subset of the full AXI protocol designed for low-throughput memory-mapped communication, such as accessing Control and Status Registers (CSRs) in peripherals like GPIO, UART, or timers.

No bursts allowed: Every transaction has a fixed burst length of exactly 1 beat.
Fixed data width: Limited strictly to 32-bit or 64-bit buses.
No out-of-order execution: Removes ID tags (AWID, ARID).
Maintains 5 channels: Preserves the independent 5-channel architecture and standard VALID/READY handshakes.

Name five special features of AXI?

Independent 5-Channel Architecture: Separates address, data, and responses into 5 distinct pathways, enabling simultaneous full-duplex read and write.
Out-of-Order Transaction Completion: Uses Transaction ID tags so faster slaves can complete ahead of slower ones.
Multiple Outstanding Addresses: Master issues new addresses before previous data phases finish, hiding latency.
Unaligned Data Access: Uses byte strobes (WSTRB) to mask valid data lanes.
Advanced Burst Modes: FIXED, INCR, and WRAP burst types.

Explain AXI read transaction

AXI Read Transaction — Signal Timeline (3-Beat Burst)

Address

Data Beats

Complete

ARVALID

ARREADY

RDATA

RVALID

RLAST

T₀

T₁

T₂

T₃

T₄

T₅

End

Address Valid Address Ready Read Data / Valid Last Beat

The Address Phase: Master asserts ARVALID, Slave asserts ARREADY. Handshake completes on the rising clock edge when both are high.
The Data Phase & Pipelining: Slave returns sequential RDATA beats with RVALID asserted. Multiple beats can flow without new address commands.
The Transaction End: Slave asserts RLAST on the final data beat, signaling burst completion.

What is the AXI capability of data interleaving?

AXI data interleaving is the capability to mix individual data beats from different transactions on the same data channel.

ID-Based Tracking: Uses Transaction ID tags (RID, WID) to identify each beat's transaction.
Rule: Beats from different IDs can be sent in any order; beats from the same ID must stay in sequence.
Benefit: Prevents a slow slave from blocking the data channel for faster transactions.

Explain out-of-order transaction support on AXI?

AXI out-of-order support allows transactions to complete in a different order from issuance, eliminating bottlenecks.

How: Uses Transaction ID tags (AWID/ARID).
Rule: Different IDs → out of order. Same ID → strict sequence.
Benefit: Slow DRAM access doesn't block fast SRAM access.

Explain multiple outstanding address pending?

The capability of an AXI master to issue new address requests before previous data phases finish.

How: Master pipes addresses on AR/AW without waiting for R/B phases.
Benefit: Hides memory latency and keeps the data bus saturated.

How to ensure data integrity on AXI?

Parity & ECC (AXI5): Native RCHK/WCHK signals carry parity or ECC bits.
Sideband USER Signals (AXI3/4): Custom CRC/parity via WUSER/RUSER.
Poison Bits (AXI5): Flag corrupted data at source to prevent bad execution.

SystemVerilog Assertion (SVA) for Handshake Dependency

If ready must come exactly 5 cycles after valid rises:

systemverilogUse code with caution.

// Property: When valid goes high, ready must be high exactly 5 cycles later
property p_valid_to_ready;
    @(posedge clk) disable iff (!rst_n)
    $rose(valid) |-> ##5 ready;
endproperty

assert_valid_to_ready: assert property (p_valid_to_ready)
    else $error("Violation: ready did not assert exactly 5 cycles after valid!");

If "within 5 cycles" is intended, change ##5 ready to ##[1:5] ready.

Q10

OoO vs Interleaving

Out-of-Order: Entire transactions complete out of sequence (different IDs).
Interleaving: Individual data beats from different bursts mix on the same channel (AXI3 only; removed in AXI4/5).

Q11

Flow control mechanisms in AXI?

VALID/READY Handshake: Transfer only when both high. VALID must stay high until READY asserts.
Credit-Based (AXI5): Receiver issues credits ahead of time, eliminating round-trip latency for long-distance links.

Q12

What is the LAST signal?

Function: Flags the final beat of a burst (WLAST for writes, RLAST for reads).
Completion: Burst finishes only when LAST, VALID, and READY are all high on the same clock edge.
AXI-Lite: LAST is removed (burst is always 1 beat).

Q13

Bursts vs Transfers

Transfer (Beat): Single data handshake on one clock edge.
Burst: Collection of multiple sequential transfers initiated by one address. Length set by AxLEN (up to 256 in AXI4).

Formula: 1 Burst = Multiple Sequential Transfers (Beats)

Q14

Maximum size of a transfer?

Up to 1024 bits (128 bytes), determined by physical bus width.

Bus Limit: Valid widths: 8, 16, 32, 64, 128, 256, 512, 1024 bits.
Control: AxSIZE (3 bits) specifies bytes per beat.
Rule: AxSIZE ≤ physical bus width.

Q15

What is strobing in AXI?

WSTRB identifies which byte lanes contain valid write data.

Mapping: Each WSTRB bit controls one byte (e.g., on 32-bit bus, WSTRB[0] → bits [7:0]).
Rule: Bit = 1 → byte is written. Bit = 0 → byte is masked.
Use Case: Enables unaligned accesses and partial-word updates without corrupting adjacent data.

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RTL DIGITAL DESIGN

Sep 30, 2026

CH : On-Chip Communication Protocols

Communication Protocols & Interfaces

4 Chapter 4: Communication Protocols

Jun 24, 2016

Interview question on AXI protocol

AXI & AHB Interview Guide

Difference between AHB and AXI?

What is AXI-Lite?

Name five special features of AXI?

Explain AXI read transaction

What is the AXI capability of data interleaving?

Explain out-of-order transaction support on AXI?

Explain multiple outstanding address pending?

How to ensure data integrity on AXI?

SystemVerilog Assertion (SVA) for Handshake Dependency

OoO vs Interleaving

Flow control mechanisms in AXI?

What is the LAST signal?

Bursts vs Transfers

Maximum size of a transfer?

What is strobing in AXI?

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