STA: Timing_Analysis: Reg to Output path analysis

Timing Analysis: Register-to-Output Path

A register-to-output path, also called a reg-to-out path, describes the timing relationship between a flip-flop inside the design and an output port of the integrated circuit or FPGA.

This analysis determines how much time is required for data launched by an internal register to become valid at an external output pin.

Basic Concept: The register captures data on an active clock edge. After the clock-to-Q delay and the output combinational delay, the data appears at the output port.

1. Register-to-Output Path Structure

Clock ───────────────► Launch Register │ │ Clock-to-Q Delay ▼ Combinational Logic │ │ Output Delay ▼ Output Port / Pin │ ▼ External Receiver

A typical register-to-output path contains the following elements:

• Launch register: Stores and launches the data.
• Clock-to-Q delay: Time taken for the register output to change after the clock edge.
• Combinational logic delay: Delay through logic between the register and output port.
• Routing delay: Delay caused by interconnects and wiring.
• Output buffer delay: Delay through the output driver or I/O cell.
• External receiver: The device or component receiving the output signal.

2. Example RTL Code

module register_to_output (
    input  wire clk,
    input  wire reset_n,
    input  wire data_in,
    output reg  data_out
);

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n)
            data_out <= 1'b0;
        else
            data_out <= data_in;
    end

endmodule

In this example, data_out is directly driven by a flip-flop. Therefore, the timing path is:

Launch Register → Output Buffer → Output Port

3. Maximum Register-to-Output Delay

The maximum delay determines the latest time at which the output data becomes valid after the active clock edge.

T_{reg-to-out(max)} = T_cq(max) + T_comb(max) + T_route(max) + T_output(max)

Where:

Parameter	Description
Tcq(max)	Maximum clock-to-Q delay of the launch register
Tcomb(max)	Maximum delay through combinational logic
Troute(max)	Maximum routing or interconnect delay
Toutput(max)	Maximum output buffer and I/O delay

Example

Assume the following delays:

• T_cq(max) = 0.20 ns
• T_comb(max) = 0.80 ns
• T_route(max) = 0.30 ns
• T_output(max) = 0.40 ns

T_{reg-to-out(max)} = 0.20 + 0.80 + 0.30 + 0.40 = 1.70 ns

Therefore, the output signal becomes valid no later than 1.70 ns after the launching clock edge.

4. Minimum Register-to-Output Delay

Minimum delay determines how quickly the output can begin changing after the active clock edge. It is important when the external receiver has a hold-time requirement.

T_{reg-to-out(min)} = T_cq(min) + T_comb(min) + T_route(min) + T_output(min)

A very small minimum delay may cause the receiving device to see new data too early, resulting in an external hold-time violation.

5. External Setup-Time Analysis

The output of one device is often connected to the input of another device. The receiving device samples the signal using its own clock.

Source Device Destination Device Launch FF ──► Logic ──► Output ──► PCB Trace ──► Input ──► Capture FF │ ▲ └── Launch Clock └── Capture Clock

For setup timing, data must arrive at the receiving device before its capture clock edge.

T_{reg-to-out(max)} + T_board(max) + T_{setup(receiver)} ≤ T_clock + T_clock-skew - T_uncertainty

If the receiving device has a clock period of 10 ns, the source register-to-output delay is 1.70 ns, the PCB delay is 0.80 ns, and the receiver setup time is 1.00 ns:

Required time = 10.00 ns
Arrival time = 1.70 + 0.80 + 1.00 = 3.50 ns
Setup slack = 10.00 - 3.50 = 6.50 ns

Positive setup slack indicates that the path meets the setup-time requirement.

6. External Hold-Time Analysis

For hold timing, the output data must not change too soon after the receiving device's capture clock edge.

T_{reg-to-out(min)} + T_board(min) ≥ T_{hold(receiver)} + T_clock-skew + T_uncertainty

If the minimum source delay is too small, new data may reach the receiving device while it is still within its hold window.

Negative hold slack indicates a hold-time violation.

7. Register-to-Output Timing in FPGA Constraints

Static timing analysis tools need external timing information. This is normally provided using an output delay constraint.

Vivado XDC Example

# Create a 100 MHz clock
create_clock -name sys_clk -period 10.000 [get_ports clk]

# Maximum output delay for setup analysis
set_output_delay -clock sys_clk -max 3.000 \
    [get_ports data_out]

# Minimum output delay for hold analysis
set_output_delay -clock sys_clk -min 1.000 \
    [get_ports data_out]

Intel Quartus SDC Example

# Create a 100 MHz clock
create_clock -name sys_clk -period 10.000 [get_ports clk]

# Maximum output delay
set_output_delay -clock sys_clk -max 3.000 \
    [get_ports data_out]

# Minimum output delay
set_output_delay -clock sys_clk -min 1.000 \
    [get_ports data_out]

Important: The values used with set_output_delay are based on the external receiver's timing requirements and board-level delays. They should not be selected arbitrarily.

8. Meaning of set_output_delay

The command below informs the timing analyzer that the external device expects the output signal to arrive within a specified time window relative to the clock.

set_output_delay -clock sys_clk -max 3.0 [get_ports data_out]

This means the output data is expected to reach the external device within 3.0 ns of the reference clock relationship used by the timing tool.

The minimum constraint is used for hold analysis:

set_output_delay -clock sys_clk -min 1.0 [get_ports data_out]

9. Timing Diagram

Clock ────┐ ┌──────┐ ┌──────┐ └──────┘ └──────┘ └── Launch FF ────●─────────────────────────────── │ │ Clock-to-Q delay ▼ Output Data ────────────────┐ └────────────────── ◄────────────► Reg-to-Output Delay Receiver ─────────────────────────●───────── │ Capture Clock Edge

10. Common Causes of Register-to-Output Violations

• Large combinational logic between the register and output.
• Excessive routing delay caused by poor placement.
• High fanout on the output-driving register.
• Slow I/O standards or incorrect drive-strength settings.
• Incorrect clock constraints.
• Missing or incorrect set_output_delay constraints.
• Clock skew and clock uncertainty.
• Long PCB traces or excessive external load capacitance.

11. Techniques to Improve Reg-to-Out Timing

Technique	Purpose
Register the output	Reduces combinational delay between the last register and output port.
Reduce combinational logic	Shortens the data path and improves maximum delay.
Use I/O registers	Places the register near the physical output pin in an FPGA.
Improve placement and routing	Reduces interconnect delay.
Reduce fanout	Prevents excessive loading on the output-driving register.
Choose a suitable I/O standard	Improves output transition time and signal integrity.
Use appropriate drive strength	Helps drive the external load without unnecessary delay or noise.

12. Registered Versus Combinational Outputs

Combinational Output

assign data_out = enable ? data_a : data_b;

The output can change whenever any input changes. The timing path may include input registers, multiplexers, logic gates, and routing.

Registered Output

always @(posedge clk) begin
    data_out <= data_next;
end

The output changes only after a clock edge. Registered outputs generally provide more predictable timing and are easier to constrain.

13. Timing Report Parameters

A static timing analysis report commonly contains:

Report Item	Meaning
Startpoint	The launching register and its clock.
Endpoint	The output port or output pin.
Data arrival time	Time taken for data to reach the output.
Data required time	Latest acceptable arrival time.
Slack	Difference between required time and arrival time.
Path delay	Total delay from the launch register to the output.

Slack = Required Time - Arrival Time

• Positive slack: Timing requirement is satisfied.
• Zero slack: Path is exactly at the timing limit.
• Negative slack: Timing violation exists.

14. Summary

• Register-to-output analysis measures the delay from an internal register to an output port.
• The maximum delay is important for external setup timing.
• The minimum delay is important for external hold timing.
• The total path includes clock-to-Q delay, logic delay, routing delay, and output-buffer delay.
• Use set_output_delay -max for setup analysis.
• Use set_output_delay -min for hold analysis.
• Positive timing slack indicates that the path meets its requirement.
• Registering outputs and reducing logic or routing delay can improve reg-to-out timing.