Digital PLL

A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal.

VCO ->  Voltage Controlled Oscillator
The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is "fed back" toward the input forming a loop.

Basic architecture of PLL -> 

There are certain limitation in digital to implement it in digital logic , one I can think of is the high frequency. To generate a target frequency , VCO may run at higher frequency which typically in Ghz and digital circuit can not run at such a high frequency. 

There are various method to do the calibration. Few of them are listed below.

1. Through binary search algorithm 

Understand it through an example. (Note -> all values/parameters are logical for understanding purpose )

Below are the parameters available. 

Ref clock -> 250 MHz  (just to make calculation simple, typical ref clock is ~100MHz) 

Target frequency and ref frequency is same, So in given time frame, counter value can be compared to adjust the voltage of VCO to increase/decrease frequency. Below is the calculation.

VCO voltage range -> 0.0 V to 5.0V  , Digital range is 8-bit value ('h0 -> 0.0 V , 'hFF -> 5.0V)

In frequency , 0.0V  -> 0hz , 5.0V -> 4 Ghz 

Target Frequency -> 250Mhz   (Target VCO voltage -> 3.5 V  ->  [2Ghz / Freq_DIV ('d8)] ) 

To start algorithm ->  Will take the middle digital value which will convert into voltage in VCO through DAC.  Signal name ->  vco_val[7:0]  

Start value vco_val ->  8'h80    ,  VCO voltage -> 2.5 V , Frequency generated by VCO -> 1.5Ghz

After Phase Detection and filter logic , 

When this value compared with ref value, result will increase frequency (means increase voltage).

Pictorial View of frequency, converging into Target Frequency.

Pros/Con for this Algorithm ->

Pros :
1. Algorithm is fast , number of iteration will be less if compared with other method.

Con :
1. Additional logic/hardware required to do the calculation.
2. Since there will be large voltage difference during 1st few iteration, this could be an issue in analog component , check with analog designer.

2. Maintaining Step size with FSM 

There could be 2 or more steps with this type of algo. Basically with a known step size (voltage increment or decrements to increase or decrease frequency in VCO ) , moving towards closure to target frequency and then reduce step size to reach more closure of target frequency. There are pros and con doing this.

Major Component in Digital PLL 

1. Phase Detector
2. Filter
3. Phase controller
4. Frequency Divider

1. Phase Detector
This block detect the phase of ref signal and output signal from frequency divider. It generate Lead/Lag signal based on the phase difference.

2 Filter
Filter is required to filter out the unwanted pulse.

3. Phase controller
Phase controller get feedback from Filter , based on the feedback , phase controller can increase or decrease the frequency and wait for next feedback.

4. Frequency Divider

Since system clock will be running at much higher frequency , To get the target frequency , frequency divider should be programmed correctly. It is normally configurable and configure at the beginning of calibration. through out calibration , it is constant. 

Verilog Code for Digital PLL

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If you have any question, please put it in comment.
Thanks for reading my blog.

Async Reset or Sync Reset for ASIC ?

Q ASYNC OR SYNC RESET? which one is use more in ASIC industry?

Async reset with sync release is probably the most common. Sync reset is used occasionally though. Async has the obvious advantage that your PoR works before the clock is working. You need a sync release to avoid potential metastability and make sure FSM start in a consistent state.

Resetting all FF's in a FPGA is not a waste of area at all. Most FPGA's come with a built in global asynchronous reset for free. It is called the CONFIG pin. You assert the pin and it puts all of the FF's into a known reset state before the clock starts. That is why you don't use FF's with an asynchronous reset in an FPGA because you don't need two complete asynchronous reset systems.

Q. Where Async reset is useful ? 

Asynchronous reset is used where logic should get reset without having any dependency on clock. In high speed design, where every clock cycle is critical, Logic has to use async reset. Latency critical design also can not afford one clock cycle delay. 

Below is the comparison between asynchronous and synchronous resets. 

Asynchronous Reset	Synchronous Reset
Flip flop area is more ..	Flip flop is less in area and less complex
A glitch on reset line can reset the whole design , extra care has to be taken.	Glitch may not effectice as reset is active on clock edge only.
Datapath is clear , no additional logic required due to reset.	Additional combinational logic required which may affect high speed datapath.
Same reset goes to thousands of flop (may be milions),  Capacitive load will be high.	Reset buffer tree may have to be pipelined to keep all resets occurring within the same clock cycle
No dependency on clock.	Clock has to be present for reset.
ASIC have expicitly reset for initialization. Asic doesn’t have any software to program.	FPGA used this type of flops as initialization happen during configuration. (all Memory/FFs will also initialize)

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Leave a comments if you have any question or doubt.

Thanks for reading it.

.lib to/from .db conversion

If you are working in DC then all library files will be in .db format , this format is nit readable by humans.

You need to convert .db file to .lib file. For that you need library compiler and license for it.

Below are the commands used to get .lib file.

Both dc_shell (Design Compiler) and Library Compiler (lc_shell)
can do this translation.

--------------------------------------------------------------------------
lc_shell> read_lib ...
lc_shell> write_lib ...

Use "read_lib", then "write_lib", of course you need a library compiler license.
You CAN NOT use those commands from DC if you
dont have a library compiler license.

Convert from .lib to .db -> 

Yes.You can use library_compiler to convert your libary from lib format to db format.
%dc_shell
dc_shell>read_lib ./path/library_file_name.lib(ex: ABCD.lib)
dc_shell>write_lib library_name -f db -o ./path/library_file_name.db

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