Below are the link for a quick review of verilog language
http://www.tcnj.edu/~hernande/Eng312/TCNJ_Verilog(R)_V05.pdf
Click on main heading for detail information.
Lexical Element
- case sensitive
- keywords - lowercase
- comments - one line comments start with " // "
- comments - more than one line - start with "/*" and end with "*/"
- variable names have to start with an alphabetic character or underscore
- system task will start from "$" character
- Parameter
- wire , wor, wand , tri0, tri1, supply0, supply1, trireg, tri, triand, trior
- reg
- integer
- time
- real
- realtime
- event
- task
- function
- input , output, input
- `define
- `ifdef , `else , `elsif , `endif
- `include
- `resetall
- `timescale
- `signed , `unsigned
- `celldefine, `endcelldefine
- `unconnected_drive pull0 | pull1
- `nounconnected_drive
- `remove_netname , `noremove_netnames
- `protect , `endprotect
- $display
- $monitor
- $strobe
- $write
- $fwrite
- $fdisplay
- $fmonitor
- $time
- $realtime
- $finish
- $showvars
- $scale
- $scope
- $showscopes
- $stop
- $setup
- $hold
- $setuphold
- $readmemb
- $readmemh
- $getpattern
and
always
assign
attribute
begin
buf
bufif0
bufif1
case
cmos
deassign
default
defparam
disable
else
endattribute
end
endcase
endfunction
endprimitive
endmodule
endtable
endtask
event
for
force
forever
fork
function
highz0
highz1
if
initial
inout
input
integer
join
large
medium
module
nand
negedge
nor
not
notif0
notif1
nmos
or
output
parameter
pmos
posedge
primitive
pulldown
pullup
pull0
pull1
rcmos
reg
release
repeat
rnmos
rpmos
rtran
rtranif0
rtranif1
scalared
small
specify
specparam
strong0
strong1
supply0
supply1
table
task
tran
tranif0
tranif1
time
tri
triand
trior
trireg
tri0
tri1
vectored
wait
wand
weak0
weak1
while
wire
wor
Source - http://www.verilog.org/verilog-ams/htmlpages/public-docs/lrm/2.3/VAMS-LRM-2-3.pdf
Parallel statement -
fork ...... join
Conditional statement -
if ..... else
if .... else if .... else
case
casez
casex
Looping statement
forever
for ( )
repeat ()
while ()
Continuous Assignment
wire abc = 5'd10 ;
assign abc = 5'd10 ;
assign a = b ;
Procedural Assignment
initial
always
task
function
Blocking Assignment
a = b ;
b = c ;
c = a ;
Non-Blocking Assignment
a <= b ;
b <= c ;
c <= a ;
$finish
$stop
$monitoron
$monitoroff
$dumpon
$dumpoff
$dumpfile
$dumplimit
$dumpflush
$dumpvars
$dumpall
$reset
$random
$realtobits
$bitstoreal
$rtoi
$itor
$display
$monitor
$strobe
$fdisply
$fmonitor
$fstrobe
$display(" Counting start - %AB " , count);
AB = d -> display in decimal
AB = h -> display in hex
AB = b -> display in binary
AB = o -> display in octal
AB = c -> display in ACSII
AB = v -> display net signal strength
AB = s -> display as string
AB = t -> display in current time format
AB = m -> display hierarchical name
AB = e -> display real in scientific form
AB = f -> display real in decimal form
AB = g -> display real in shortest form
Waveform dump using $dump system task -
Syntax -
$dumpfile(<filename>);
$dumpvars(<levels> <,<module|var>>* );
$dumpoff;
$dumpon;
$dumpall;
$dumplimit(<filesize>);
$dumpflush;
The $dumpfile system task specifies the name of the value change dump file.
The $dumpvars system task specifies the variables whose changing values a tool records in the value change dump file. The $dumpvars when invoked with no arguments dumps all variables in the design.
The $dumpoff system task stops a tool from recording value changes in the value change dump file.
The $dumpon system task allows a tool to resume recording value changes in the value change dump file.
The $dumpall system task creates a checkpoint that shows the current value of all variables being recorded in the value change dump file.
The $dumplimit system task sets the size of the value change dump file.
The $dumpflush system task empties the dump file buffer and ensures that all the data in that buffer is stored in the value change dump file.
initial begin
$dumpvar(<file>.wave);
$dumpvars(); // dump all
end
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