RTL DIGITAL DESIGN

Practical ASIC , RTL , VLSI Knowledge

Sep 29, 2026

Verification Quizzes

Posted by VLSI Expert - Rahul J No comments:
Email ThisBlogThis!Share to XShare to FacebookShare to Pinterest
Newer Posts Older Posts Home
Subscribe to: Posts (Atom)

ChipDesign.Expert

ChipDesign.Expert
RJ
Rahul Jain
VLSI / RTL Design Blog
chipdesign.expert rahulj0in
Follow for VLSI & RTL design tips

About Me

VLSI Expert - Rahul J
View my complete profile

Digital Design Blog

Digital Design Blog
This blog is on Digital design , includes other related topics.

Blog_Insider

  • Career Growth In Vlsi Industry
  • Semiconductor Job portal - Internship
  • VLSI world for Freshers
  • Future of Semiconductor
  • VLSI Projects
  • PLL or DLL
  • Complex Number
  • Serial Perepheral Interface
  • UART Design
  • I2C Design
  • How to make Digital PLL
  • Reset - Async or Sync ?
  • How to convert .db to .lib
  • How to verify Mixed signal design
  • Know about unateness
  • RTL technique for Low Power Design
  • Unified Power Format - UPF for Low Power
  • UPF Example
  • Refreshing Verilog for Interview
  • Low Power Design and Verification
  • Blocking and Non Blocking in Verilog
  • Gate Level Simulation
  • Code Coverage Analysis
  • BIST
  • Static Timing Analysis
  • SDC - Timing Constraint
  • Debugging Guideline for Functional Simulation
  • Clock Dividers and Multipliers
  • Correct way of Digital design RTL Coding
  • Digital Design for Beginner and Prof
  • Clock Gating Circuits
  • Handling multiclock domain in design ( RTL + SDC )
  • Implementation of Logical Questions
  • Step by Step approach to make XOR using NAND
  • APTITUDE QUESTIONS
  • Interview Questions on AXI
  • Edge detection logic with Verilog code
  • Gvim Help
  • Error Detection and Correction
  • Running Disparity
  • Verilog Code for the counting number of 1's and 0's
  • Verilog code for binary to gray code
  • Verilog Code for FIR Filter
  • Types of Adders with Verilog Code
  • VHDL Operator
  • Parameter in Verilog
  • SpyGlass Custom Goal
  • Dump Synchronizer using SpyGlass
  • Generic Interview Questions
  • Resume Guidelines - A must visit page
  • Analog IC Design
  • Left -Edge Algorithm
  • Max Transition Violation in Design
  • OCV, AOCV and POCV -Static Timing Analysis
  • you-need-to-remove-these-6-items
  • FREE CAD Tools
  • List of Semiconductor Comanies
  • The best top 20 universities for MS in Digital VLSI in USA

Top Visited Posts

  • VLSI Projects
  • 100+ VLSI Digital interview questions
  • Roadmap For Educational Projects in VLSI

RTL Code

  • RTL for Asynchronous FIFO
  • RTL for cnt 0's n 1's
  • RTL for FIR Filter
  • RTL for Bin2Gray
  • RTL for 8-bit ALU
  • SPI Controller RTL code in Verilog
  • RTL for Pos/Neg Detector
  • RTL for Parity Checker
  • RTL Design for Gray to Binary
  • RTL for calculate square root
  • RTL for Round Robin Algo

Blog Archive

Blog Posts

1. Pattern Detection 2. Gray to Binary code 3. FIR Filter 4. Round Robin Algorithm 5. LED converter 6. Binary to Gray 7. Synchronous FIFO

Search This Blog

Disable

All rights reserved, copyright to Rahul Jain. Theme images by TommyIX. Powered by Blogger.