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VLSI Expert - Rahul J

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Digital Design Blog

This blog is on Digital design , includes other related topics.

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PLL or DLL
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How to make Digital PLL
Reset - Async or Sync ?
How to convert .db to .lib
How to verify Mixed signal design
Know about unateness
RTL technique for Low Power Design
Unified Power Format - UPF for Low Power
UPF Example
Refreshing Verilog for Interview
Low Power Design and Verification
Blocking and Non Blocking in Verilog
Gate Level Simulation
Code Coverage Analysis
BIST
Static Timing Analysis
SDC - Timing Constraint
Debugging Guideline for Functional Simulation
Clock Dividers and Multipliers
Correct way of Digital design RTL Coding
Digital Design for Beginner and Prof
Clock Gating Circuits
Handling multiclock domain in design ( RTL + SDC )
Implementation of Logical Questions
Step by Step approach to make XOR using NAND
APTITUDE QUESTIONS
Interview Questions on AXI
Edge detection logic with Verilog code
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Error Detection and Correction
Running Disparity
Verilog Code for the counting number of 1's and 0's
Verilog code for binary to gray code
Verilog Code for FIR Filter
Types of Adders with Verilog Code
VHDL Operator
Parameter in Verilog
SpyGlass Custom Goal
Dump Synchronizer using SpyGlass
Generic Interview Questions
Resume Guidelines - A must visit page
Analog IC Design
Left -Edge Algorithm
Max Transition Violation in Design
OCV, AOCV and POCV -Static Timing Analysis
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The best top 20 universities for MS in Digital VLSI in USA

RTL Code

RTL for Asynchronous FIFO
RTL for cnt 0's n 1's
RTL for FIR Filter
RTL for Bin2Gray
RTL for 8-bit ALU
RTL for Parity Checker
RTL for Pos/Neg Detector
RTL Design for Gray to Binary
RTL for calculate square root
RTL for Round Robin Algo

Blog Posts

1. Pattern Detection 2. Gray to Binary code 3. FIR Filter 4. Round Robin Algorithm 5. LED converter 6. Binary to Gray 7. Synchronous FIFO

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Jan 14, 2022

Grade 7 - Math's - Test Paper 2 - Multi-choice

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