Digital Design - Expert Advise
Enhance knowledge in Digital VLSI domain - By Rahul Jain
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VERILOG_RTL
Count 0's n 1's
SYNC n ASYNC FF
Pattern Detection
GREY TO BINARY CONV
FIR FILTER
PARITY CHECKER
SQUARE ROOT
ROUND ROBIN ALGO
BINARY TO 7-SEGMENT
8-BIT ALU
BINARY TO GREY CONV
SYNCHRONOUS FIFO
EDGE DETECTOR
LOW Power Design
Low Power Design Verification
Low Power design Technique
RTL for Low Power Design
UPF for Low Power DesignLink 3
UPF Example
Retention Cells UPF
Link 3
Digital Design
Reset Recovery and Removal
NAND Gate using Mux
Async or Synchronous Reset for Asic
XOR gate using NAND
Error Correction n Detection
AHB or AXI or AMBA 2
I2C or CAN Protocol
MTBF
Link 3
Link 2
Link 3
Link 2
Link 3
Synthesis
SDC File
Samir Palnitkar Solution
Timing Constraint
Clock Gating Circuit
Interview Question
Target Library Vs Link Library
Link 2
Protocol
I2C IP
UART IP
SPI IP
MicroWire IP
Link 2
Link 2
Link 2
VLSI Quiz
Quiz 1: Digital design Fundamentals
Quiz2: Digital Design: CDC
Link 1
Interview QA
VLSI Interview Q/A
Interview Q/A on AXI Protocol
Interview Q/A on Digital Design
Interview Q/A General Topics
Interview Q/A on PCIe Express
Interview Q/A on Synthesis
Interview Q/A on IC Fabrication
Interview Q/A on Asynchronous FIFO
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Jan 15, 2022
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