Digital Design: Clock Gate Design : How to make glitch free logic for clock gating circuit ?

Integrated Clock Gating (ICG) Architecture & Automation

A manual combinational gate (like a standalone AND gate) will cause structural clock glitches if the enable signal transitions while the clock pulse is active. To achieve a glitch-free implementation, the industry-standard architecture maps a level-sensitive latch to filter out raw enable hazards before they reach the gating gate.

1. Why the Circuit is Glitchless

For positive-edge triggered downstream sequential logic, the Integrated Clock Gating (ICG) cell combines a negative level-sensitive latch with a 2-input AND gate. The filtering functionality is divided across two distinct phases of the clock:

• When CLK is High (Logic 1): The negative latch is completely opaque (latched). Even if the functional enable (EN) transitions or suffers from parasitic spikes, the latch output (LATCH_Q) is locked. Because LATCH_Q is completely static, the AND gate cleanly passes the high clock phase without clipping or glitching.
• When CLK is Low (Logic 0): The negative latch transitions to transparent, letting the new state of EN drive LATCH_Q. Any glitches on EN will pass through to LATCH_Q during this time. However, because the second pin of the AND gate is forced to 0 by the low clock line, the ultimate output (GATED_CLK) remains anchored to ground, absorbing the glitch safely.

2. Functional Behavioral Waveform

The timeline below highlights how an irregular or hazard-prone enable line gets filtered into a perfectly formed, clean gated clock output.

__ __ __ __ __ __ CLK __| |____| |____| |____| |____| |____| |____ _________________________ EN _____| |__________________ (Erratic/Glitchy Enable) _________________ LATCH_Q _________| |______________________ (Latched cleanly at CLK=0) __ __ GATED_CLK _________| |____| |____________________________ (Clean Clock Pulses) ^ ^ ^ |________|________|--> Clean falling/rising edges

3. SystemVerilog RTL Modeling

The structural layout of an explicit ICG element includes an integrated OR path for structural Scan/DFT testing overrides.

module glitch_free_icg (
    input  logic clk,       // Source Clock
    input  logic en,        // Functional Enable Signal
    input  logic te,        // Test Enable (for scan testing/DFT)
    output logic gated_clk  // Safe Gated Clock Output
);

    logic latch_d;
    logic latch_q;

    // OR gate combines functional enable and DFT test enable
    assign latch_d = en | te;

    // Negative level-sensitive latch modeling
    // The latch passes data when clk is 0, and holds its state when clk is 1
    always_latch begin
        if (!clk) begin
            latch_q <= latch_d;
        end
    end

    // Clock gating structural AND gate
    assign gated_clk = clk & latch_q;

endmodule

4. Critical Constraints & Timing Rules

Static Timing Analysis (STA) engines treat the gating pin of an ICG as a sequential endpoint. The tools check two specific windows relative to the falling edge of the clock:

• Gating Setup Check: Ensures that a changing EN signal settles at the latch input before the clock falls (the latch's locking edge). If data arrives too late, the latch risks capturing an unstable value, leading to a clipped or missing leading-edge clock pulse.
• Gating Hold Check: Ensures that the EN signal stays perfectly stable for a minimum duration after the clock falls. If the enable line drops to zero too quickly right on the falling clock edge, a narrow runt pulse can squeeze past the latch before it completely closes its transparency window.

SDC Custom Setup & Hold Verification Syntax:
Standard Cell Foundries embed these parameters within the .lib files. If you use custom macros or basic logical gates, you must enforce explicit checks via your Synopsys Design Constraints (SDC) file:

# Enforce specific setup/hold safety guard bands on custom logic structures
set_clock_gating_check -setup 0.200 -hold 0.100 [get_cells i_glitch_free_icg/u_and_gate]
set_clock_gating_check -high [get_cells i_glitch_free_icg/u_and_gate]
set_gated_clock_cells [get_cells i_glitch_free_icg]

5. Automated Synthesis Insertion Scripts

Modern ASIC workflows leverage the synthesis tool to automatically parse RTL, find synchronous enable code, and map it directly to structural library ICG cells.

A. Synopsys Design Compiler (DC) Script Configuration

###############################################################################
# Design Compiler - Automatic Clock Gating Insertion Setup
###############################################################################

set_clock_gating_style -sequential_cell latch \
                       -positive_edge_logic {integrated} \
                       -negative_edge_logic {integrated} \
                       -control_point before \
                       -control_signal scan_enable \
                       -minimum_bitwidth 4 \
                       -max_fanout 32

# Elaborate, Link, and Map Gating Structural Blocks
elaborate my_design
link
insert_clock_gating
compile_ultra -gate_clock

# Output Structural Metrics