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Showing posts with label
verilog
.
Show all posts
Showing posts with label
verilog
.
Show all posts
Feb 23, 2025
Cyclic Redundancy Check (CRC) Generator - RTL Code
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A Cyclic Redundancy Check (CRC) is a popular error-detection technique used in communication protocols and file storage systems to check fo...
May 3, 2021
Tips to start a Academic project from scratch to completion
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Many students ask , what are the steps to start a academic project , I understand , many people like to learn many things , for example , bu...
Dec 28, 2016
Verilog Code for Round Robin Algorithm
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Round Robin algorithm details : Round Robin algorithm Verilog code : What is Round Robin algorithm ? Round-robin (RR) is one of the a...
5 comments:
Dec 20, 2016
Verilog code square root of a number
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Verilog code to calculate the square root of a number -> ------------------Start of Verilog Code -------------------- `timescale 1n...
4 comments:
Parameterized Modules in Verilog
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How to pass parameter in verilog design from the top module ? There are different method to do that , when a module is instantiate with ...
Sep 27, 2016
Verilog Code for 8-bit ALU
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/* *inst[3:0] = 4'h0 => reserved *inst[3:0] = 4'h1 => Addition *inst[3:0] = 4'h2 => Substraction *inst...
2 comments:
Dec 8, 2015
Selective Signal dumping in VPD VCS
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Q. How to dump waveform using command line option in VCS ? initial begin $vcspluson(); end If you are trying to dump VCD form...
143 comments:
Aug 27, 2014
Verilog Introduction
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Verilog is a HDL language, HDL – Hardware Description Language , which means any digital hardware can be described by verilog language. I...
Jun 15, 2014
Verilog - Reserved KeyWords
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always starts an always begin ... end sequential code block and gate primitive, and assign parallel continuou...
Jun 1, 2014
Verilog Operators
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Verilog HDL operators are same as in C language. {} - concatenation usage - reg ab; reg [1:0] cd ; reg [2:0] z ; always @(*) ...
May 10, 2014
Verilog - System Task
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$bitstoreal Convert bits into real number. Syntax wire [64:1] abc; real num = $bitstoreal(abc); $countdrivers The $countdrivers ...
1 comment:
Refreshing your brain with Verilog
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Below are the link for a quick review of verilog language http://www.tcnj.edu/~hernande/Eng312/TCNJ_Verilog(R)_V05.pdf Click on main h...
Mar 24, 2014
Verilog Design Style
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Verilog HDL allow users to go for design either bottom up or top down. Bottom up - The traditional method of electronic design is bott...
90 comments:
Verilog - Statements
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Parallel statement - fork ...... join Conditional statement - if ..... else if .... else if .... else case casez ...
Mar 22, 2014
Verilog - Data Types
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Verilog HDL consists of 4 basic values - 0 - Logic zero 1 - Logic one x - unknown value z -high-impedance state value z and x are sa...
Mar 12, 2014
How simulator executes blocking and non-blocking statement in Verilog
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We all know that there are blocking statements and non-blocking statements , If I ask what is blocking and what is non-blocking , the fir...
1 comment:
Mar 4, 2014
Verilog - Lexical Element
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Lexical -- it means related to the language, here will describe in more detail about the lexical elements in verilog. Convention Overvi...
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