UPF Quiz : On Power Switch

📘 UPF Power-Up Sequence Quiz

UPF Power-Up & Power Switch Quiz

1. What is the main purpose of a power switch in UPF?
Increase frequency
Reduce leakage power
Improve timing

2. Which signal controls a power switch?
Clock
Reset
Enable signal

3. Isolation is required because:
To save dynamic power
To prevent X propagation
To reduce area

4. What is the correct first step during power-up?
Enable clock
Disable isolation
Keep isolation ON

5. Power-good (PG) signal indicates:
Clock stable
Voltage is stable
Reset released

6. When should retention restore happen?
After clock enable
Before clock enable
After isolation OFF

7. Clock should be enabled:
Before power ON
After reset release
During power ramp

8. Header power switch uses:
NMOS
PMOS
Transmission gate

9. Footer power switch is placed near:
VDD
VSS
Clock tree

10. What happens if clock is ON before power?
No issue
Short-circuit current
Lower leakage

11. Isolation is disabled only after:
Power OFF
Clock OFF
Full domain stabilization

12. What avoids inrush current?
Fast enable
Staggered power switches
Clock gating

13. Retention registers are used to:
Clamp outputs
Save state during power OFF
Improve timing

14. Which UPF element defines power gating?
create_clock
create_power_switch
set_false_path

15. Correct power-up order is:
Clock → Power → Isolation OFF
Isolation → Power → Clock
Reset → Clock → Power

Comment if you got 15/15

Quiz-2 on Digital Design Fundamentals 

Quiz-1 on Digital Design Fundamentals